8K x 8 Static RAM
f
ax
id
:
1013

CY7C185

CypressSemiconductor Corporation • 3901North First Street • SanJose • CA 95134 • 408-943-2600
Au
g
ust 12
,
1998

Features

• High speed
—15 ns
• Fast tDOE
• Low active power
—715 mW
• Low standby power
—220 mW
• CMOS for optimum speed/power
• Easy memory expansio n with CE1, CE2, and OE fe atures
• TTL-compatible inputs and outputs
• Automatic power-down when deselected

Functional Description

The CY7C185 is a high-performance CMOS static RAM orga-
nized as 8192 words by 8 bits. Easy memory expansion is
provided by an active LOW chip enable (CE1), an act iv e HIGH
chip enable (CE2), and active LOW output enable (OE) and
three-state drivers. This device has an automatic power-do wn
feature (CE1 or CE2), reducing the power consumpti on by 70%
when deselected. The CY7C185 is in a standard 300-mi l-wi de
DIP, SOJ, or SOIC package.
An active LOW write enable signal (WE) controls the writ-
ing/reading operation of the memory. When CE1 and WE in-
puts are both LOW and CE2 is HIGH, data on the eight data
input/output pins (I/O0 through I/O7) is written into t he memory
location addressed by the address present on the address
pins (A0 through A12). Reading the device is accomplished by
selecting the device and enabling the outputs, CE1 and OE
active LOW, CE2 active HIGH, while WE remains inactive or
HIGH. Under these conditions, the conte nts of the lo catio n ad-
dressed by the information on address pins are pr ese nt on t he
eight data input/output pins.
The input/output pins remain in a high-impedance sta te unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH. A die coat is used to insure alpha immunity.

Logic Block Diagram Pin Configurations

C185–1
A1
A2
A3
A4
A5
A6
A7
A8
A0
A10
A9
A11
A12
I/O0
C185–2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
CE2
A3
A2
A1
OE
A0
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
NC
A4
A5
A6
A7
A8
A9
A10
A11
A12
I/O0
I/O1
I/O2
GND
256 x 32 x 8
ARRAY
INPUT BUFFER
COLUMN DECODER
ROW DECODER
SENSE AMPS
POWER
DOWN
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
CE1
CE2
WE
OE
Top View
DIP/SOJ/SOIC
Selection Guid e[1]
7C185–15 7C185–20 7C185–25 7C185–35
Maximum Access Time (ns) 15 20 25 35
Maximum Operating Current (mA) 130 110 100 100
Maximum Standby Current (mA) 40/15 20/15 20/15 20/15
Note:
1. For military specifications, see the CY7C185A datasheet.