CY7C1855
Switching Waveforms
9. Device is continuously selected. OE, CE1 = VIL. CE2 = VIH.
10. WE is HIGH for read cycle.
11. Data I/O is High Z if OE = VIH, CE1 = VIH, WE = VIL, or CE2=VIL.
12. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. CE 1 and WE must be LOW and CE2 must be HIGH
to initiate write. A write can be terminated by CE1 or WE going HIGH or CE2 going LOW. The data input set-up and hold timing should be referenced to the
rising edge of the signal that terminates the write.
13. During this period, the I/Os are in the output state and input signals should not be applied.
ADDRESS
DATA OUT PREVIOUS DATA VALID DATA VALID
tRC
tAA
tOHA
C185–6
Read Cycle No.1[9,10]
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE IMPEDANCE
ICC
ISB
tHZOE tHZCE
tPD
OE
HIGH
DATA OUT
VCC
SUPPLY
CURRENT
CE1
OE
CE2
C185–7
Read Cycle No.2[11,12]
C185–8
tHD
tSD
tPWE
tSA
tHA
tAW
tWC
tHZOE
DATAIN VALID
CE
CE1
OE
WE
CE2
DATA I/O
tSCEI
tSCE2
ADDRESS
NOTE 13
[10,12]