Cypress CY7C185 Switching Waveforms

CY7C185

Notes:

14. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.

15. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in a hi gh-impedance state.

Switching Waveforms (continued)

tWC

tAW

tSA

tHA

tHD

tSD

tSCE1

DATA I/O

ADDRESS

CE1

C185–9

DATAIN VALID

tSCE2

CE2

W

rite Cycle No. 2 (CE Controlled)[12,13,14]

tHD

tSD

tLZWE

tSA

tHA

tAW

tWC

tHZWE C185–10

DATA INVALID

tSCE1

tSCE2

CE1

CE2

ADDRESS

DATA I/O

Write Cycle No. 3 (WE Controlled, OE LOW)[12,13,14,15]

NOTE 13

Contents

Main 8K x 8 Static RAM CY7C185 Features Functional Description Logic Block Diagram Pin Configurations Maximum Ratings Operating Range Electrical Characteristics Capacitance AC Test Loads and Waveforms Switching Characteristics CY7C185 Switching Waveforms Write Cycle No. 1 (WE Controlled) Read Cycle No.1 Read Cycle No.2 Switching Waveforms W rite Cycle No. 2 (CE Controlled) Write Cycle No. 3 (WE Controlled, OE LOW) CY7C185 Typical DC and AC Characteristics CY7C185 Truth Table Address Designators Ordering Information