CY7C185

Switching Characteristics Over the Operating Range[5]

 

 

 

 

 

 

 

7C185–15

7C185–20

7C185–25

7C185–35

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Parameter

 

 

 

 

 

Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Unit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

READ CYCLE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tRC

 

Read Cycle Time

15

 

20

 

25

 

35

 

ns

tAA

 

Address to Data Valid

 

15

 

20

 

25

 

35

ns

tOHA

 

Data Hold from

3

 

5

 

5

 

5

 

ns

 

 

Address Change

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tACE1

 

 

1

LOW to Data Valid

 

15

 

20

 

25

 

35

ns

CE

tACE2

 

CE2

HIGH to Data Valid

 

15

 

20

 

25

 

35

ns

tDOE

 

 

 

 

LOW to Data Valid

 

8

 

9

 

12

 

15

ns

OE

tLZOE

 

 

 

 

LOW to Low Z

3

 

3

 

3

 

3

 

ns

OE

t

 

 

 

 

HIGH to High Z[6]

 

7

 

8

 

10

 

10

ns

OE

HZOE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

t

 

 

 

 

 

LOW to Low Z[7]

3

 

5

 

5

 

5

 

ns

CE

1

LZCE1

 

 

 

 

 

 

 

 

 

 

 

 

tLZCE2

 

CE2

HIGH to Low Z

3

 

3

 

3

 

3

 

ns

t

 

 

 

 

 

HIGH to High Z[6, 7]

 

7

 

8

 

10

 

10

ns

CE

1

HZCE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CE2

LOW to High Z

 

 

 

 

 

 

 

 

 

tPU

 

 

1

LOW to Power-Up

0

 

0

 

0

 

0

 

ns

CE

 

 

CE2 to HIGH to Power-Up

 

 

 

 

 

 

 

 

 

tPD

 

 

1

HIGH to Power-Down

 

15

 

20

 

20

 

20

ns

CE

 

 

CE2 LOW to Power-Down

 

 

 

 

 

 

 

 

 

WRITE CYCLE

[8]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tWC

 

Write Cycle Time

15

 

20

 

25

 

35

 

ns

tSCE1

 

 

1

LOW to Write End

12

 

15

 

20

 

20

 

ns

CE

tSCE2

 

CE2

HIGH to Write End

12

 

15

 

20

 

20

 

ns

tAW

 

Address Set-Up to

12

 

15

 

20

 

25

 

ns

 

 

Write End

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tHA

 

Address Hold from

0

 

0

 

0

 

0

 

ns

 

 

Write End

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tSA

 

Address Set-Up to

0

 

0

 

0

 

0

 

ns

 

 

Write Start

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tPWE

 

 

 

 

Pulse Width

12

 

15

 

15

 

20

 

ns

WE

tSD

 

Data Set-Up to Write End

8

 

10

 

10

 

12

 

ns

tHD

 

Data Hold from Write End

0

 

0

 

0

 

0

 

ns

t

 

 

 

 

LOW to High Z[6]

 

7

 

7

 

7

 

8

ns

WE

HZWE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tLZWE

 

 

 

 

HIGH to Low Z

3

 

5

 

5

 

5

 

ns

WE

Notes:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5.Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance.

6.tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady state voltage.

7.At any given temperature and voltage condition, tHZCE is less than tLZCE1 and tLZCE2 for any given device.

8.The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, and WE LOW. All 3 signals must be active to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.

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Cypress CY7C185 specifications Switching Characteristics Over the Operating Range5, CE2