32K x 8 Static RAM

CY7C199

CypressSemiconductor Corporation • 3901North FirstStreet • SanJose • CA 95134 • 408-943-2600
Document #: 38-05160 Rev. ** Revised September 7, 2001
99

Features

• High speed
—10 ns
•Fast t
DOE
• CMOS for optimum speed/power
• Low active power
—467 mW (max, 12 ns “L” version)
• Low standby power
—0.275 mW (max, “L” version)
• 2V data retention (“L” version only)
• Easy memory expansion with CE and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected

Functional Description

The CY7C199 is a high-performance CMOS static RAM orga-
nized as 32,768 words by 8 bits. Easy memory ex pansion is
provided by an active LOW Chip Enable (CE) and active LOW
Output Enable (OE) and three-state drivers. This device has
an automatic power-down feature, reducing the power con-
sumption by 81% when deselected. The CY7C199 is in the
standard 300-mil-wide DIP, SOJ, and LCC packages.
An active LOW Write Enable signal (WE) controls the writ-
ing/reading operation of the memory. When CE and WE inputs
are both LOW, data on the eight data input/output pins (I/O0
through I/O7) is written into the memory location addressed by
the address present on the address pins (A0 through A14).
Reading the device is accomplished by sel ecting the d evice
and enabling the outputs, CE and OE active LOW, while WE
remains inactive or HIGH. Under these conditions, the con-
tents of the location addressed by the information on address
pins are present on the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and Write Enable
(WE) is HIGH. A die coat is used to improve alpha immunity.

Selection Guide

7C199-8 7C199-10 7C199-12 7C199-15 7C199-20 7C199-25 7C199-35 7C199-45
Maximum Access Time (ns) 81012 15 20 25 35 45
Maximum Operating
Current (mA) 120 110 160 155 150 150 140 140
L90 90 90 90 80 70
Maximum CMOS
Standby Current (mA) 0.5 0.5 10 10 10 10 10 10
L0.05 0.05 0.05 0.05 0.05 0.05
Shaded area contains advance information.

Logic Block Diagram Pin Configurations

A1
A2
A3
A4
A5
A6
A7
A8
COLUMN
DECODER
ROW DECODER
SENSE AMPS
INPUTBUFFER
POWER
DOWN
WE
OE
I/O0
CE
I/O1
I/O2
I/O3
1
2
3
4
5
6
7
8
9
10
11
14 15
16
20
19
18
17
21
24
23
22
Top Vie w
DIP / SOJ / SOIC
12
13
25
28
27
26
GND
A6
A7
A8
A9
A10
A11
A12
A13
WE
VCC
A4
A3
A2
A1
I/O7
I/O6
I/O5
I/O4
A14
A5
I/O0
I/O1
I/O2
CE
OE
A0
I/O3
1024x 32 x 8
ARRAY
I/O7
I/O6
I/O5
I/O4
A9
A0
A
11
A
13
A
12
A
14
A
10
28
4
5
6
7
8
9
10
321 27
1314151617
26
25
24
23
22
21
20
11
12 19
18
A7
V
CC
I/O5
GND
WE
A6
A5
I/O4
I/O3
I/O2
A8
A9
A10
A11
A12
A13
A14 CE
A3
A2
A1
A0
I/O1
I/O7
I/O6
A4
OE
I/O0
Top Vie w
LCC
C199–1
C199–2
C199–3
22
23
24
25
26
27
28
1
2
510
11
15
14
13
12
16
19
18
17
3
4
20
21
7
6
8
9
OE
A1
A2
A3
A4
WE
VCC
A5
A6
A7
A8
A9
A0
CE
I/O7
I/O6
I/O5
GND
I/O2
I/O1
I/O4
I/O0
A14
A10
A11 A13
A12
C199–4
I/O3
TSOP I
Top Vie w
(not to scale)