CY7C199
Document #: 38-05160 Rev. ** Page 5 of 16
Switching Characteristics Over the Operating Range[3, 7]
7C199-8 7C199-10 7C199-12 7C199-15
UnitParameter Description Min. Max. Min. Max. Min. Max. Min. Max.
READ CYCLE
tRC Read Cycle Time 810 12 15 ns
tAA Address to Data Valid 8 101215ns
tOHA Data Hold from Address Change 3333ns
tACE CE LOW to Data Valid 8101215ns
tDOE OE LOW to Data Valid 4.5 5 5 7 ns
tLZOE OE LOW to Low Z[8] 0000ns
tHZOE OE HIGH to High Z[8, 9] 5557ns
tLZCE CE LOW to Low Z[8] 3333ns
tHZCE CE HIGH to High Z[8,9] 4557ns
tPU CE LOW to Power-Up 0000ns
tPD CE HIGH to Power-Down 8 101215ns
WRITE CYCLE[10, 11]
tWC Write Cycle Time 810 12 15 ns
tSCE CE LOW to Write End 77910ns
tAW Address Set-Up to Write End 77910ns
tHA Address Hold from Write End 0000ns
tSA Address Set-Up to Write Start 0000ns
tPWE WE Pulse Width 7789ns
tSD Data Set-Up to Write End 5589ns
tHD Data Hold from Write End 0000ns
tHZWE WE LOW to High Z[9] 5677ns
tLZWE WE HIGH to Low Z[8] 3333ns
Shaded area contains advance informatio n.
Notes:
7. Test conditions assume signal transition time of 3 ns or less for -12 and -15 speeds and 5 ns or less for -20 and slower speeds, timing reference levels of 1.5V,
input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance.
8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
9. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±50 0 mV from s teady- state vo ltage.
10. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initi ate a write a nd either sig nal can term inate
a write by going HIGH. The data input set-up and hold timing should be referen ced t o the ri sing edge of t he si gnal tha t termi nates the write.
11. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW ) is th e sum o f tHZWE and tSD.