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Cypress CY7C1392BV18, CY7C1992BV18, CY7C1393BV18, CY7C1394BV18 manual 250

Models: CY7C1393BV18 CY7C1392BV18 CY7C1992BV18 CY7C1394BV18

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CY7C1392BV18, CY7C1992BV18

CY7C1393BV18, CY7C1394BV18

Ordering Information (continued)

Not all of the speed, package, and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered.

Speed	Ordering Code	Package	Package Type	Operating
(MHz)	Ordering Code	Diagram	Package Type	Range
250	CY7C1392BV18-250BZC	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)	Commercial

	CY7C1992BV18-250BZC

	CY7C1393BV18-250BZC

	CY7C1394BV18-250BZC

	CY7C1392BV18-250BZXC	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

	CY7C1992BV18-250BZXC

	CY7C1393BV18-250BZXC

	CY7C1394BV18-250BZXC

	CY7C1392BV18-250BZI	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)	Industrial

	CY7C1992BV18-250BZI

	CY7C1393BV18-250BZI

	CY7C1394BV18-250BZI

	CY7C1392BV18-250BZXI	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

	CY7C1992BV18-250BZXI

	CY7C1393BV18-250BZXI

	CY7C1394BV18-250BZXI

200	CY7C1392BV18-200BZC	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)	Commercial

	CY7C1992BV18-200BZC

	CY7C1393BV18-200BZC

	CY7C1394BV18-200BZC

	CY7C1392BV18-200BZXC	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

	CY7C1992BV18-200BZXC

	CY7C1393BV18-200BZXC

	CY7C1394BV18-200BZXC

	CY7C1392BV18-200BZI	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)	Industrial

	CY7C1992BV18-200BZI

	CY7C1393BV18-200BZI

	CY7C1394BV18-200BZI

	CY7C1392BV18-200BZXI	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

	CY7C1992BV18-200BZXI

	CY7C1393BV18-200BZXI

	CY7C1394BV18-200BZXI

Document #: 38-05623 Rev. *D

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Cypress CY7C1392BV18, CY7C1992BV18, CY7C1393BV18, CY7C1394BV18 manual 250

Contents

Selection Guide FeaturesConfigurations Functional DescriptionLogic Block Diagram CY7C1392BV18 CLKDoff Array Gen Read Data Reg Control Logic Block Diagram CY7C1393BV18Logic Block Diagram CY7C1394BV18 512KCY7C1992BV18 2M x Pin ConfigurationBall Fbga 13 x 15 x 1.4 mm Pinout CY7C1392BV18 2M xCY7C1394BV18 512K x CY7C1393BV18 1M xPin Definitions Pin Name Pin DescriptionSynchronous Read/Write Input. When TDO for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device Is Referenced with Respect toFunctional Overview Shows four DDR-II SIO used in an application Application ExampleComments Truth TableWrite Cycle Descriptions OperationInto the device. D359 remains unaltered Write cycle description table for CY7C1992BV18 followsWrite cycle description table for CY7C1394BV18 follows DeviceIeee 1149.1 Serial Boundary Scan Jtag Idcode State diagram for the TAP controller follows TAP Controller State DiagramTAP Electrical Characteristics TAP Controller Block DiagramTAP Timing and Test Conditions TAP AC Switching CharacteristicsRegister Name Bit Size Identification Register DefinitionsScan Register Sizes Instruction CodesBit # Bump ID Boundary Scan OrderPower Up Sequence in DDR-II Sram Power Up SequenceDLL Constraints Electrical Characteristics DC Electrical CharacteristicsMaximum Ratings AC Electrical Characteristics Input High Voltage Vref +Input LOW Voltage Vref Document # 38-05623 Rev. *D Parameter Description Test Conditions Fbga Unit CapacitanceThermal Resistance Parameter Description Test Conditions Max UnitLOW Switching CharacteristicsParameter Min Max HighDLL Timing Parameter Min Max Output TimesBurst Switching WaveformsOrdering Information 250 167 Ball Fbga 13 x 15 x 1.4 mm Package DiagramDocument History SYTNXR USB Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions VKN/PYRS