Cypress CY7C68321C, CY7C68320C Quad Flat Package No Leads QFN Package Design Notes, PCB Material

CY7C68300C/CY7C68301C

CY7C68320C/CY7C68321C

Quad Flat Package No Leads (QFN) Package Design Notes

Electrical contact of the part to the Printed Circuit Board (PCB) is made by soldering the leads on the bottom surface of the package to the PCB. Hence, special attention is required to the heat transfer area below the package to provide a good thermal bond to the circuit board. A Copper (Cu) fill must be designed into the PCB as a thermal pad under the package. Heat is transferred from the AT2LP through the device’s metal paddle on the bottom side of the package. Heat from here is conducted to the PCB at the thermal pad. It is then conducted from the thermal pad to the PCB inner ground plane by a 5 x 5 array of vias. A via is a plated through-hole in the PCB with a finished diameter of 13 mil. The QFN’s metal die paddle must be soldered to the PCB’s thermal pad. Solder mask is placed on the board top side over each via to resist solder flow into

the via. The mask on the top side also minimizes outgassing during the solder reflow process.

For further information on this package design, refer to the application note Surface Mount Assembly of AMKOR’s MicroLeadFrame (MLF) Technology. The application note provides detailed information on board mounting guidelines, soldering flow, rework process, etc.

Figure 15 displays a cross-sectional area underneath the package. The cross section is of only one via. The solder paste template needs to be designed to allow at least 50% solder coverage. The thickness of the solder paste template must be 5 mil. It is recommended that ’No Clean,’ type 3 solder paste is used for mounting the part. Nitrogen purge is recommended during reflow.

Figure 15. Cross-Section of the Area Under the QFN Package

0.017” dia

Solder Mask

Cu Fill

Cu Fill

PCB Material

Via hole for thermally connecting the QFN to the circuit board ground plane.

0.013” dia

PCB Material

This figure only shows the top three layers of the circuit board: Top Solder, PCB Dielectric, and the Ground Plane

Figure 16 is a plot of solder mask pattern and Figure 17 displays an X-Ray image of assembly (darker areas indicate solder).

Figure 16. Plot of the Solder Mask (White Area) Figure 17. X-Ray Image of the Assembly

Other Design Considerations

Certain design considerations must be followed to ensure proper operation of the CY7C68300C/CY7C68301C. The following items must be taken into account when designing a USB device with the CY7C68300C/CY7C68301C.

Proper Power Up Sequence

Power must be applied to the CY7C68300C/CY7C68301C before, or at the same time as the ATA/ATAPI device. If power is supplied to the drive first, the CY7C68300C/CY7C68301C startup in an undefined state. Designs that utilize separate power supplies for the CY7C68300C/CY7C68301C and the ATA/ATAPI device are not recommended.

Document 001-05809 Rev. *A Page 40 of 42

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