CY7C68300C/CY7C68301C
CY7C68320C/CY7C68321C
Pin Diagrams
The AT2LP is available in different package types to meet a variety of design needs. The CY7C68320C/321C is available in
Figure 2.
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DD13 |
|
|
| DD12 |
DD14 |
|
|
| DD11 |
DD15 |
|
|
| DD10 |
GND |
|
|
| DD9 |
ATAPUEN (GND) |
| DD8 | ||
VCC |
|
| (ATA_EN) VBUS_ATA_ENABLE | |
GND |
|
|
| VCC |
IORDY |
|
|
| RESET# |
DMARQ |
|
| GND | |
AVCC |
|
| ARESET# | |
XTALOUT |
| (VBUS_PWR_VALID) DA2 | ||
XTALIN |
|
|
| CS1# |
AGND |
|
|
| CS0# |
VCC |
|
| (DA2) DRVPWRVLD | |
DPLUS |
|
| DA1 | |
|
|
| ||
DMINUS |
| CY7C68300C | DA0 | |
GND |
|
| INTRQ | |
|
| CY7C68301C | ||
VCC |
|
| VCC | |
GND |
|
|
| DMACK# |
PWR500# (PU 10K) | DIOR# | |||
GND (Reserved) |
| DIOW# | ||
SCL |
|
|
| GND |
SDA |
|
|
| VCC |
VCC | NOTE: Labels in italics denote pin functionality | GND | ||
| during CY7C68300A compatibility mode. | |||
DD0 |
| DD7 | ||
|
|
| ||
DD1 |
|
|
| DD6 |
DD2 |
|
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| DD5 |
DD3 |
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| DD4 |
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Document | Page 3 of 42 |
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