Cypress CY7C68300C/CY7C68301C, CY7C68320C/CY7C68321C, Chip reset See “RESET#” on page

								CY7C68300C/CY7C68301C
								CY7C68320C/CY7C68321C
	Table 1. AT2LP Pin Descriptions
		Note: (Italic pin names denote pin functionality during CY7C68300A compatibility mode) (continued)
	100	56	56		Pin Name	Pin	Default State	Pin Description
	TQFP	QFN	SSOP			Type	at Startup
	68	34	41		DA0	O/Z[1]	Driven HIGH	ATA address.
							after 2 ms
							delay
	69	35	42		DA1	O/Z[1]	Driven HIGH	ATA address.
							after 2 ms
							delay
	70[3]	36[3]	43	DRVPWRVLD		I	Input	Device presence detect. (See “DRVPWRVLD” on
					(DA2)			page 13). Configurable logical polarity is controlled by
								EEPROM address 0x08. This pin must be pulled HIGH
								if functionality is not utilized.
								Alternate function. Input when the EEPROM configu-
								ration byte 8 has bit 7 set to one. The input value is
								reported through EP1IN (byte 0, bit 0).
	71	37	44		CS0#	O/Z[1]	Driven HIGH	ATA chip select.
							after 2 ms
							delay
	72	38	45		CS1#	O/Z[1]	Driven HIGH	ATA chip select.
							after 2 ms
							delay
	73	39	46		DA2	O/Z[1]	Driven HIGH	ATA address.
				(VBUS_PWR_VALID)			after 2 ms
							delay
	74	40	47		ARESET#	O/Z[1]		ATA reset.
	75	41	48		GND	GND		Ground.
	76	N/A	N/A		NC	NC		No connect.
	77	42	49		RESET#	I	Input	Chip reset (See “RESET#” on page 14).
	78	43	50		VCC	PWR		VCC. Connect to 3.3V power source.
	79	44	51	VBUS_ATA_ENABLE		I	Input	VBUS detection (See “VBUS_ATA_ENABLE” on
					(ATA_EN)			page 14).
	80	45	52		DD8	IO[1]	Hi-Z	ATA data bit 8.
	81	46	53		DD9	IO[1]	Hi-Z	ATA data bit 9.
	82	47	54		DD10	IO[1]	Hi-Z	ATA data bit 10.
	83	48	55		DD11	IO[1]	Hi-Z	ATA data bit 11.
	84	N/A	N/A		GND			Ground.
	85	N/A	N/A		VCC	PWR		VCC. Connect to 3.3V power source.
	86	N/A	N/A		NC	NC		No connect.
	87
	88	36[3]	N/A		GPIO0	IO[3]		General purpose IO pins (See “GPIO Pins” on
	89	13[3]			GPIO1			page 13). The GPIO pins must be tied to GND if
	90	54[3]			GPIO2			functionality is not used.
	91				GPIO3
	92				GPIO4
	93				GPIO5
	94	N/A	N/A		GND	GND		Ground.
	95	49	56		DD12	IO[1]	Hi-Z	ATA data bit 12.
	96	50	1		DD13	IO[1]	Hi-Z	ATA data bit 13.
	97	51	2		DD14	IO[1]	Hi-Z	ATA data bit 14.
	98	52	3		DD15	IO[1]	Hi-Z	ATA data bit 15.
	99	53	4		GND	GND		Ground.
Document 001-05809 Rev. *A								Page 10 of 42

[+] Feedback