CY7C68300C/CY7C68301C
CY7C68320C/CY7C68321C
Table 8. Example CfgCB
Offset | CfgCB Byte Descriptions |
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| 7 | 6 | 5 | 4 |
| 3 | 2 | 1 | 0 |
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0 | bVSCBSignature (set in configuration bytes) | 0 | 0 | 1 | 0 |
| 0 | 1 | 0 | 0 |
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1 | bVSCBSubCommand (must be 0x26) | 0 | 0 | 1 | 0 |
| 0 | 1 | 1 | 0 |
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2 | Reserved (must be set to zero) | 0 | 0 | 0 | 0 |
| 0 | 0 | 0 | 0 |
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3 | Data Source (must be set to 0x02) | 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 0 |
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4 | Start Address (LSB) (must be set to zero) | 0 | 0 | 0 | 0 |
| 0 | 0 | 0 | 0 |
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5 | Start Address (MSB) (must be set to zero) | 0 | 0 | 0 | 0 |
| 0 | 0 | 0 | 0 |
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Reserved (must be set to zero) | 0 | 0 | 0 | 0 |
| 0 | 0 | 0 | 0 | |
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MfgCB
The mfg_load and mfg_read
The data transfer length is determined by the CBW Data Transfer Length specified in bytes 8 through 11 (dCBWDataTransferLength) of the CBW. The type and direction of the command is determined by the direction bit specified in byte 12, bit 7 (bmCBWFlags) of the CBW.
Table 9. Example MfgCB
Offset |
| MfgCB Byte Description |
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| Bits |
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | bVSCBSignature | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 |
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| (set in configuration bytes) |
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1 | 1 | bVSCBSubCommand | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 |
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| (hardcoded 0x27) |
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0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
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Mfg_load
During a Mfg_load, the AT2LP enters into Manufacturing Test Mode. Manufacturing Test Mode is provided as a means to implement board or system level interconnect tests. During Manufacturing Test Mode operation, all outputs not directly associated with USB operation are controllable. Normal control of the output pins are disabled. Control of the select AT2LP IO pins and their
Mfg_read
This USB request returns a ’snapshot’ of select AT2LP input pins. AT2LP input pins not directly associated with USB operation can be sampled at any time during Manufacturing Test Mode operation. See Table 10 for an explanation of the Mfg_read data format. Any data length can be specified, but only bytes 0 through 3 contain usable information, so a length of 4 bytes is recommended.
Table 10.Mfg_read and Mfg_load Data Format
Byte | Bits | Read/Load | Function |
0 | 7 | R/L | ARESET# |
| 6 | R | DA2 |
| 5:4 | R/L | CS#[1:0] |
| 3 | R/L | DRVPWRVLD |
| 2:1 | R/L | DA[1:0] |
| 0 | R | INTRQ |
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1 | 7 | L | DD[15:0] |
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| 0 = |
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| 1 = Drive DD pins |
| 6 | R | MFG_SEL |
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| 0 = Mass Storage Mode |
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| 1 = Manufacturing Mode |
| 5 | R | VBUS_ATA_ENABLE |
| 4 | R | DMARQ |
| 3 | R | IORDY |
| 2 | R/L | DMACK# |
| 1 | R/L | DIOR# |
| 0 | R/L | DIOW# |
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2 | 7:0 | R/L | DD[7:0] |
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3 | 7:0 | R/L | DD[15:8] |
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Document | Page 20 of 42 |
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