PRELIMINARY
EZ-USB HX2LP
™
Low-Power USB 2.0 Hub Controller Fam
ily
CY7C656x
x
CypressSemiconductor Corporation • 3901North First Street • SanJose, CA 95134 • 408-943-2600
Document #: 38-08037 Rev. *D Revised March 31, 2005

1.0 Features

• USB 2.0 hub controller
• Compliant with the USB 2.0 specification
•Windows Hardware-quality lab (WHQL)-compliant
• Up to four downstream ports supported
• Supports bus-power and self powered modes
• Single-TT and Multi-TT modes supported
—Single-TT option for low-cost
—Multi-TT option for high performance
•2-Port
—Single TT option for bus power
•Fit/form/function compatible option with CY7C65640
(TetraHub)
• Multiple package options
—Space-saving 56 QFN
• Single power supply requirement
—Internal regulator for reduced cost
• Integrated upstream pull-up resistor
• Integrated pull-down resistors for all downstream ports
• Integrated upstream and downstream termination
resistors
• Integrated port status indicator controls
• 24-MHz external crystal (integrated PLL)
• Configurable with external SPI EEPROM
—Vendor ID, Product ID, Device ID (VID/PID/DID)
—Number of active ports
—Number of removable ports
—Maximum power setting for high-speed and full-
speed
—Hub controller power setting
—Power-on timer
—Overcurrent detection mode
—Overcurrent timer
—Enable/Disable overcurrent timer
—Overcurrent pin polarity
—indicator pin polarity
—Compound device
—Enable full-speed only
—Disable port indicators
—Gang power switching
—Enable single-TT mode only
—Self/bus powered compatibility
—Fully configurable string descriptors for multiple
language support
• In-system EEPROM programming

2.0 Introduction

EZ-USB HX2LP is Cypress’s next-generation family of high-
performance, low-power USB 2.0 hub controllers. HX2LP is an
ultra low-power single-chip USB 2.0 hub controller with
integrated upstream and downstream transceivers, a USB
Serial Interface Engine (SIE), USB Hub Control and Repeater
logic, and Transaction Translator (TT) logi c. Cypr ess has al so
integrated many of the external passive components, such as
pull-up and pull-down resistors, reducing the overall bill-of-
materials required to implement a hub design. The entire
HX2LP portfolio consists of:
1.CY7C65640B (TetraHub LP): 4-port/multiple transaction
translator
This device option is fit/form/function compatible with Cy-
press’s existing CY7C65640 device. Cypress’s “Tetra” ar-
chitecture provides four downstream USB ports, each with
a dedicated Transaction Translator ( TT), making it the h igh-
est-performance hub available. The TetraHub LP also of-
fers best-in-class power consumption. The CY7C65640B is
available in a 56 QFN (TetraHub pin-comp atible) for space
saving designs.
2.CY7C65630: 4-port/single transaction translator
This device option is for ultra low-cost applications where
performance is secondary consideration. All four ports
must share a single transaction translator in this configura-
tion. The CY7C65630 is available in a 56 QFN and is also
pin for pin-compatible with the CY7C65640.
3.CY7C65620:
This device option is for a 2-port bus powered application.
Both ports must shar e a single transaction translator in th is
configuration. The CY7C65620 is available in a 56 QFN
and is also pin for pin compatible with the CY7C65640.
All device options are supported by Cypress’s world-class
reference design kits, which include board schematics, bill of
materials, Gerber files, Orcad files, and thorough design
documentation.