Cypress STK11C68 manual Pin Configurations, Pin Definitions

STK11C68

Pin Configurations

Figure 1. Pin Diagram - 28-Pin SOIC/DIP and 28-Pin LLC

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Pin Definitions

Pin Name

Alt

IO Type

Description

A0–A12

Input

Address Inputs. Used to select one of the 8,192 bytes of the nvSRAM.

DQ0-DQ7

Input or

Bidirectional Data IO Lines. Used as input or output lines depending on operation.

Output

Input

Write Enable Input, Active LOW. When the chip is enabled and

is LOW, data on the

WE

WE

W

IO pins is written to the specific address location.

Input

Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the

CE

E

chip.

Input

Output Enable, Active LOW. The active LOW

input enables the data output buffers

OE

OE

G

during read cycles. Deasserting OE HIGH causes the IO pins to tri-state.

VSS

Ground

Ground for the Device. The device is connected to ground of the system.

VCC

Power Supply

Power Supply Inputs to the Device.

Document Number: 001-50638 Rev. ** Page 2 of 16

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