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| STK11C68 | ||
Software Controlled STORE/RECALL Cycle |
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The software controlled STORE/RECALL cycle follows. [10, 11] |
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| Parameter |
| Alt |
| Description | 25 ns | 35 ns | 45 ns | Unit | |||
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| Min | Max | Min | Max | Min | Max | ||||
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tRC | tAVAV | STORE/RECALL Initiation Cycle Time | 25 |
| 35 |
| 45 |
| ns | |||
t | [10] | t | AVEL | Address Setup Time | 0 |
| 0 |
| 0 |
| ns | |
| SA |
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tCW[10] | tELEH | Clock Pulse Width | 20 |
| 25 |
| 30 |
| ns | |||
tHACE[10] | tELAX | Address Hold Time | 20 |
| 20 |
| 20 |
| ns | |||
tRECALL[10] |
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| RECALL Duration |
| 20 |
| 20 |
| 20 | μs | ||
Switching Waveform
Figure 10. CE Controlled Software STORE/RECALL Cycle [11]
ADDRESS
CE
OE
DQ (DATA)
tRC
ADDRESS # 1
tSA |
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| tSCE |
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tHACE
DATA VALID
tRC
ADDRESS # 6
tSTORE / tRECALL
HIGH IMPEDANCE
DATA VALID
Notes
10.The software sequence is clocked on the falling edge of CE without involving OE (double clocking aborts the sequence).
11.The six consecutive addresses must be read in the order listed in Table 1 on page 4. WE must be HIGH during all six consecutive cycles.
Document Number: | Page 10 of 16 |
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