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AC Switching Characteristics |
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SRAM Read Cycle |
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Parameter | Description | 25 ns | 35 ns | 45 ns | Unit | |||||
Cypress | Alt | Min | Max | Min | Max | Min |
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Parameter |
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tACE | tELQV | Chip Enable Access Time |
| 25 |
| 35 |
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| 45 | ns |
tRC [4] | tAVAV, tELEH | Read Cycle Time | 25 |
| 35 |
| 45 |
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| ns |
tAA [5] | tAVQV | Address Access Time |
| 25 |
| 35 |
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| 45 | ns |
tDOE | tGLQV | Output Enable to Data Valid |
| 10 |
| 15 |
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| 20 | ns |
tOHA [5] | tAXQX | Output Hold After Address Change | 5 |
| 5 |
| 5 |
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| ns |
tLZCE [6] | tELQX | Chip Enable to Output Active | 5 |
| 5 |
| 5 |
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| ns |
tHZCE [6] | tEHQZ | Chip Disable to Output Inactive |
| 10 |
| 13 |
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| 15 | ns |
tLZOE [6] | tGLQX | Output Enable to Output Active | 0 |
| 0 |
| 0 |
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| ns |
tHZOE [6] | tGHQZ | Output Disable to Output Inactive |
| 10 |
| 13 |
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| 15 | ns |
tPU [3] | tELICCH | Chip Enable to Power Active | 0 |
| 0 |
| 0 |
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| ns |
tPD [3] | tEHICCL | Chip Disable to Power Standby |
| 25 |
| 35 |
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| 45 | ns |
Switching Waveforms
Figure 5. SRAM Read Cycle 1: Address Controlled [4, 5]
$''5(66
W5&
W$$
W2+$
'4 '$7$287 
'$7$9$/,'
Figure 6. SRAM Read Cycle 2: CE and OE Controlled [4]
$''5(66
&(
2(
'4 '$7$287
,&&
W5&
W$&(
W/=&(
W'2(
W/=2(
W38 
$&7,9(
67$1'%<
W3'
W+=&(
W+=2(
'$7$9$/,'
Notes
4.WE must be High during SRAM Read cycles.
5.I/O state assumes CE and OE < VIL and WE > VIH; device is continuously selected.
6.Measured ±200 mV from steady state output voltage.
Document Number: | Page 7 of 16 |
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