Cypress STK11C68 manual Sram Write Cycle

								STK11C68
SRAM Write Cycle
	Parameter		Description	25 ns		35 ns		45 ns		Unit
Cypress		Alt		Min	Max	Min	Max	Min	Max
Parameter
tWC		tAVAV	Write Cycle Time	25		35		45		ns
tPWE		tWLWH, tWLEH	Write Pulse Width	20		25		30		ns
tSCE		tELWH, tELEH	Chip Enable To End of Write	20		25		30		ns
tSD		tDVWH, tDVEH	Data Setup to End of Write	10		12		15		ns
tHD		tWHDX, tEHDX	Data Hold After End of Write	0		0		0		ns
tAW		tAVWH, tAVEH	Address Setup to End of Write	20		25		30		ns
tSA		tAVWL, tAVEL	Address Setup to Start of Write	0		0		0		ns
tHA		tWHAX, tEHAX	Address Hold After End of Write	0		0		0		ns
tHZWE [6,7]		tWLQZ	Write Enable to Output Disable		10		13		15	ns
tLZWE [6]		tWHQX	Output Active After End of Write	5		5		5		ns

Switching Waveforms

Figure 7. SRAM Write Cycle 1: WE Controlled [7, 8]

	tWC
ADDRESS
	tSCE
CE
	tAW
	tSA
WE	tPWE
	tSD
DATA IN	DATA VALID
	tHZWE
	HIGH IMPEDANCE

DATA OUT PREVIOUS DATA

tHA

tHD

tLZWE

ADDRESS

CE

WE

DATA IN

Figure 8. SRAM Write Cycle 2: CE and OE Controlled [7, 8]

tWC

tSA tSCE tHA

tAW

tPWE

tSD tHD

DATA VALID

DATA OUT

Notes

HIGH IMPEDANCE

7.If WE is Low when CE goes Low, the outputs remain in the high impedance state.

8.CE or WE must be greater than VIH during address transitions.

Document Number: 001-50638 Rev. ** Page 8 of 16

[+] Feedback