Enterasys Networks manual NEW FEATURES AND ENHANCEMENTS IN E9.1.7.0, Å New Line, Page 17 of

Models: E9.1.7.0

1 31
Download 31 pages 34.92 Kb
Page 17
Image 17
Display of the System FPGA Revision

NEW FEATURES AND ENHANCEMENTS IN E9.1.7.0

Display of the System FPGA Revision

A capability has been added that permits the display of the system FPGA revision number as illustrated in the example below.

SYSTEM# system show hardware

 

Hardware Information

:

 

 

System type

:

ER16, Rev. 0

 

CPU Module type

: CPU-ER16 (CM4), Rev. 0

 

Processor

: R7000, Rev 3.2, 380.00 MHz

 

Icache size

: 16 Kbytes, 32 bytes/line

 

Dcache size

: 16 Kbytes, 32 bytes/line

 

CPU Board frequency

:

95.00 MHz

 

Backplane frequency

:

62.50 MHz

 

System FPGA

:

Rev. 20

Å New Line

Switching Fabrics

: 1 (Active = Fabric 2)

 

PCMCIA card

: 32MB flash memory card (mounted on slot0: or slot1:)

 

System Memory size

:

256 Mbytes

 

Network Memory size

:

256 Mbytes

 

MAC Addresses

 

 

 

System

:

0001f4:c2ff6d

 

10Base-T CPU Port

:

0001f4:c2ff6e

 

Internal Use

:

0001f4:c2ff6f -> 0001f4:c2ffac

 

CPU Mode

:

Active

 

Redundant CPU slot

:

Not present

 

10/02/03 P/N: 9038090-53

Subject to Change Without Notice

Page: 17 of 31

F0615-J

Page 17
Image 17
Enterasys Networks manual NEW FEATURES AND ENHANCEMENTS IN E9.1.7.0, Display of the System FPGA Revision, Å New Line