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Fairchild FPF2300, FPF2302, FPF2303 Figure 31. Current Limit Response Time Both, Channels are in OC, Figure 32. Startup FLAGB Blanking Time, Figure 33. Inrush Response During Capacitive Load

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Typical Characteristics

	IN	IN = 5V
	5V/DIV	IN = 5V
	5V/DIV	ON = 3.3V
		ON = 3.3V
	ON	COUTA = 100μF
	ON	COUTB = 100μF
	2V/DIV	RLA = RLB = 1Ω
	OUTA
	2V/DIV
	OUTB
	2V/DIV
		400μs/DIV

Figure 31. Current Limit Response Time Both

Channels are in OC

	IN	IN = 5V
	5V/DIV	IN = 5V
	5V/DIV	ON = 3.3V
		ON = 3.3V
	ON	COUTA = 100μF
	ON	COUTB = 100μF
	2V/DIV	RLA = RLB = 1Ω
	FLAGB(A)
	2V/DIV
	FLAGB(B)
	2V/DIV
		10ms/DIV

Figure 32. Startup FLAGB Blanking Time

Limit Current Output-Dual — FPF2300/02/03

IN

5V/DIV

ON

5V/DIV

IOUT

500mA/DIV

OUT

5V/DIV

IN = 5V

COUT = 47μF

CL = 470μF

RL = 5Ω

1ms/DIV

	IN	IN = 5V
	5V/DIV	IN = 5V
	5V/DIV	CIN = 10μF
		CIN = 10μF
	ON	COUT = 100μF
	ON	CL = 47μF
	5V/DIV
	IOUT
	2A/DIV
	OUT
	5V/DIV
		200μs/DIV

Switch

Figure 33. Inrush Response During Capacitive Load

Hot Plug-In Event

Figure 34. Inrush Response During Capacitive and

Resistive Load Hot Plug-In Event

© 2009 Fairchild Semiconductor Corporation	www.fairchildsemi.com
FPF2300/02/03 • Rev. 1.1.3	10

Contents

Figure 1. 8-LeadSOP Figure 2. 8-LeadMLP (3x3mm) Minimum Current Limit Auto ON Pin PartNumber Current Eco Figure 3. Typical Application Figure 4. Block Diagram Figure 5. Pin Configurations Pin # Name Function Symbol Parameter Min Max Unit Page Page Page Page Page Page On/Off Control Figure 35. FLAGB Assertion in Under-VoltageFault Current Limiting Fault Reporting Figure 36. FPF2300 FLAGB Reports While Entering Input Capacitor Figure 37. FPF2300 FLAGB While and Over-Current Condition is Applied Under-VoltageLockout (UVLO) Reverse Current Blocking Figure 38. Self Powered 4-PortUSB Hub Using a Single FPF230X Figure 39. Individual Port Power Management for Self-Powered 4-PortUSB Hub Figure 40. Self-PoweredUSB Port for High Current Demand Power Dissipation Improving Thermal Performance Figure 41. Two Through-HoleOpen Vias Embedded in DAP Figure 42. Proper Layout of Output and Ground Copper Area Figure 44. Bottom and ASB Layers Figure 43. Top, SST and AST Layers (MLP 3x3mm and SO8) Figure 45. Zoom-Into Top Layer Figure 46. 8-LeadSO8 Package Figure 47. 8-LeadMolded Leadless Package (MLP)