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Fairchild FPF2300, FPF2302, FPF2303 Figure 25. tOFF Response, Figure 27. Startup FLAGB Blanking Time (FPF2303), Figure 29. Current Limit at Startup with, Different Output Capacitor

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Typical Characteristics

IN

2V/DIV

ON

2V/DIV

	IN = 5V
OUT	ON = 3.3V
OUT	COUT = 0.1μF
2V/DIV	RL = 500Ω
	200μs/DIV
	Figure 25. tOFF Response

COUT = 10μF

ONRL = 3.3Ω 2V/DIV

tSTART_BLANK

FLAGB 2V/DIV

IOUT

1A/DIV

OUT

2V/DIV

2ms/DIV

Figure 27. Startup FLAGB Blanking Time (FPF2303)

	IN	IN = 5V
	5V/DIV	ON = 3.3V
	ON	RL = 5Ω
	ON	COUT = 470μF
	5V/DIV	COUT = 470μF
	IOUT
	1A/DIV	COUT = 220μF
		COUT = 220μF
		COUT = 100μF
		COUT = 47μF
		200μs/DIV

Figure 29. Current Limit at Startup with

Different Output Capacitor

		IN = 5V
		COUT = 10μF
ON		RL = 2.8Ω
2V/DIV	tBLANK

FLAGB 2V/DIV

IOUT

1A/DIV

OUT

5V/DIV

2ms/DIV

Figure 26. Over-Current Blanking Time (FPF2300/2)

ON	tRSTRT
2V/DIV	tRSTRT
FLAGB
2V/DIV
IOUT
1A/DIV		IN = 5V
OUT		IN = 5V
OUT		COUT = 10μF
5V/DIV		RL = 2.8Ω
	100ms/DIV

Figure 28. Auto-Restart Time (FPF2300)

	IN		IN = 5V
	5V/DIV		IN = 5V
	5V/DIV		ON = 3.3V
			ON = 3.3V
	ON		RL = 5Ω
	ON
	5V/DIV
	OUT	COUT = 47μF	COUT = 220μF
	OUT	COUT = 100μF	COUT = 470μF
	5V/DIV	COUT = 100μF	COUT = 470μF

200μs/DIV

Figure 30. Output Voltage at Startup with

Different Output Capacitor

Switch Limit Current Output-Dual — FPF2300/02/03

© 2009 Fairchild Semiconductor Corporation	www.fairchildsemi.com
FPF2300/02/03 • Rev. 1.1.3	9

Contents

Figure 1. 8-LeadSOP Figure 2. 8-LeadMLP (3x3mm) Minimum Current Limit Auto ON Pin PartNumber Current Eco Figure 3. Typical Application Figure 4. Block Diagram Figure 5. Pin Configurations Pin # Name Function Symbol Parameter Min Max Unit Page Page Page Page Page Page On/Off Control Figure 35. FLAGB Assertion in Under-VoltageFault Current Limiting Fault Reporting Figure 36. FPF2300 FLAGB Reports While Entering Input Capacitor Figure 37. FPF2300 FLAGB While and Over-Current Condition is Applied Under-VoltageLockout (UVLO) Reverse Current Blocking Figure 38. Self Powered 4-PortUSB Hub Using a Single FPF230X Figure 39. Individual Port Power Management for Self-Powered 4-PortUSB Hub Figure 40. Self-PoweredUSB Port for High Current Demand Power Dissipation Improving Thermal Performance Figure 41. Two Through-HoleOpen Vias Embedded in DAP Figure 42. Proper Layout of Output and Ground Copper Area Figure 44. Bottom and ASB Layers Figure 43. Top, SST and AST Layers (MLP 3x3mm and SO8) Figure 45. Zoom-Into Top Layer Figure 46. 8-LeadSO8 Package Figure 47. 8-LeadMolded Leadless Package (MLP)