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Fairchild FPF2300, FPF2302, FPF2303 Figure 44. Bottom and ASB Layers, Figure 43. Top, SST and AST Layers, (MLP 3x3mm and SO8), Figure 45. Zoom-Into Top Layer

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FPF230X Evaluation Board

The FPF230X evaluation board has components and circuitry to demonstrate FPF2300/2/3 load switch functions and features, accommodating both the MLP 3x3mm and SO8 packages. The state of the each channel can be configured using J1 and J2 jumpers. In addition, both channels can be controlled by ONA and ONB test pints. Thermal performance of the board is improved using techniques in the layout recommendations section. R3 and R4 resistors are used on the board to sink a light load current when switches are activated.

Figure 44. Bottom and ASB Layers

Figure 43. Top, SST and AST Layers

(MLP 3x3mm and SO8)

Figure 45. Zoom-In to Top Layer

Releated Resources

FPF2300/02/03 Evaluation Board User Guide; Power Switch for USB Applications

Switch Limit Current Output-Dual — FPF2300/02/03

© 2009 Fairchild Semiconductor Corporation	www.fairchildsemi.com
FPF2300/02/03 • Rev. 1.1.3	16

Contents

Figure 1. 8-LeadSOP Figure 2. 8-LeadMLP (3x3mm) Minimum Current Limit Auto ON Pin PartNumber Current Eco Figure 3. Typical Application Figure 4. Block Diagram Figure 5. Pin Configurations Pin # Name Function Symbol Parameter Min Max Unit Page Page Page Page Page Page On/Off Control Figure 35. FLAGB Assertion in Under-VoltageFault Current Limiting Fault Reporting Figure 36. FPF2300 FLAGB Reports While Entering Input Capacitor Figure 37. FPF2300 FLAGB While and Over-Current Condition is Applied Under-VoltageLockout (UVLO) Reverse Current Blocking Figure 38. Self Powered 4-PortUSB Hub Using a Single FPF230X Figure 39. Individual Port Power Management for Self-Powered 4-PortUSB Hub Figure 40. Self-PoweredUSB Port for High Current Demand Power Dissipation Improving Thermal Performance Figure 41. Two Through-HoleOpen Vias Embedded in DAP Figure 42. Proper Layout of Output and Ground Copper Area Figure 44. Bottom and ASB Layers Figure 43. Top, SST and AST Layers (MLP 3x3mm and SO8) Figure 45. Zoom-Into Top Layer Figure 46. 8-LeadSO8 Package Figure 47. 8-LeadMolded Leadless Package (MLP)