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Fairchild FPF2300, FPF2302, FPF2303 Pin #, Name, Function, Figure 5. Pin Configurations

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Pin Configuration

							FLAGB(A)						GND

GND	1				8	FLAGB(A)		8				1
IN						OUTA	OUTA						IN

	2				7			7				2
ONA						OUTB				9
										9
	3				6		OUTB	6				3	ONA
ONB						FLAGB(B)
	4				5
	4				5		FLAGB(B)	5				4	ONB
							FLAGB(B)	5				4	ONB


							MLP 3X3mm 8-Lead Bottom View
			SO8				MLP 3X3mm 8-Lead Bottom View
				Figure 5. Pin Configurations

Pin Description

	Pin #	Name	Function

	1	GND	Ground

	2	IN	Supply Input: Input to the power switch and the supply voltage for the IC.

	3	ONA	ON / OFF control input of power switch A. Active LOW

	4	ONB	ON / OFF control input of power switch B. Active LOW

	5	FLAGB(B)	Fault Output B, Active LO, open drain output which indicates an over supply, UVLO
	5	FLAGB(B)	and thermal shutdown.
			and thermal shutdown.

	6	OUTB	Switch Output: Output of the power switch B

	7	OUTA	Switch Output: Output of the power switch A

	8	FLAGB(A)	Fault Output A, Active LO, open drain output which indicates an over supply, UVLO
	8	FLAGB(A)	and thermal shutdown.
			and thermal shutdown.
	9(MLP)	Thermal Pad	IC Substrate, which can be connected to GND for better thermal performance. Do not
	9(MLP)	Thermal Pad	connect to other pins.

Switch Limit Current Output-Dual — FPF2300/02/03

© 2009 Fairchild Semiconductor Corporation	www.fairchildsemi.com
FPF2300/02/03 • Rev. 1.1.3	3

Contents

Figure 1. 8-LeadSOP Figure 2. 8-LeadMLP (3x3mm) Minimum Current Limit Auto ON Pin PartNumber Current Eco Figure 3. Typical Application Figure 4. Block Diagram Figure 5. Pin Configurations Pin # Name Function Symbol Parameter Min Max Unit Page Page Page Page Page Page On/Off Control Figure 35. FLAGB Assertion in Under-VoltageFault Current Limiting Fault Reporting Figure 36. FPF2300 FLAGB Reports While Entering Input Capacitor Figure 37. FPF2300 FLAGB While and Over-Current Condition is Applied Under-VoltageLockout (UVLO) Reverse Current Blocking Figure 38. Self Powered 4-PortUSB Hub Using a Single FPF230X Figure 39. Individual Port Power Management for Self-Powered 4-PortUSB Hub Figure 40. Self-PoweredUSB Port for High Current Demand Power Dissipation Improving Thermal Performance Figure 41. Two Through-HoleOpen Vias Embedded in DAP Figure 42. Proper Layout of Output and Ground Copper Area Figure 44. Bottom and ASB Layers Figure 43. Top, SST and AST Layers (MLP 3x3mm and SO8) Figure 45. Zoom-Into Top Layer Figure 46. 8-LeadSO8 Package Figure 47. 8-LeadMolded Leadless Package (MLP)