Fujitsu FR60 3. Operating mode conditions

185

Chapter 12 Instruction Cache

3.Operating mode conditions

3. Operating mode conditions

●Cache status in various operating modes

The table below indicates the prevailing state for disable and flush when the associated bit is

changed by bit manipulation instruction, etc.

Immediately

after a Reset Disable (FNAB=0) Flushed

Cache Memory Contents

undefined The preceding state is held.

Rewritingis impossible while

the cache is disabled.

The preceding state is held.

Tag Address

Tag Contents

undefined The preceding state is held.

Rewriting is impossible while

the cache is disabled.

The preceding state is held.

Sub-block

Valid Bit Contents

undefined The preceding state is held.

Rewritingis impossible while

the cache is disabled.

The preceding state is held.

LRU Bit Contents

undefined The preceding state is held.

Rewritingis impossible while

the cache is disabled.

The preceding state is held.

Entry Lock

Bit Contents

undefined The preceding state is held.

Rewritingis impossible while

the cache is disabled.

The preceding state is held.

(entry lock release is required)

TAG Valid

Bit Contents

undefined The preceding state is held.

Flushingispossible while the

cache is disabled.

All entries are invalid.

RAM Normal Mode The precedingstate is held.

Flushing is possible while

the cache is disabled.

The preceding state is held.

Control

Lock Unlock The preceding state is held.

Rewriting is possible while

the cache is disabled.

The preceding state is held.

Auto lock

Fail No fail Thepreceding state is held.

Rewriting is possible while

the cache is disabled.

The preceding state is held.

Entry Auto

Lock Unlock The preceding state is held.

Rewriting is possible while

the cache is disabled.

The preceding state is held.

Entry Lock

Release No release The preceding state is held.

Rewriting is possible while

the cache is disabled.

The preceding state is held.

Enable Disable Disabled The preceding state is held.

Flush Not flushed Thepreceding state is held.

Rewriting is possible while

the cache is disabled.

Flushed in cycle following

memory accessing.

Reverts to 0 subsequently.

Contents

Main Page Page -i 2004 FUJITSU LIMITED Printed in Japan TOC Chapter 2 MB91460 Rev.A/Rev.B Overview..................................................... 11 Chapter 3 MB91460 Series Basic Information................................................. 23 Chapter 6 EIT: Exceptions, Interrupts and Traps.......................................... 121 Page Page Chapter 20 Software Watchdog Timer.............................................................. 273 Chapter 21 Hardware Watchdog Timer ............................................................ 283 Chapter 22 Main Oscillation Stabilisation Timer............................................. 289 Chapter 23 Sub Oscillation Stabilisation Timer............................................... 299 Page Page Chapter 39 Programmable Pulse Generator.................................................... 795 Chapter 40 Pulse Frequency Modulator........................................................... 823 Page Page Page Page 1 Chapter 1 Introduction 1. How to Handle the Device Device Handling Instructions This chapter describes latch-up prevention and pin termination. To set latch-up prevention Page 2. Instruction for Users Clock Controls Switching of dual-purpose port Low-power-consumption mode Power-on sequence Caution: PS register Watchdog timer function Register against read/modify/write command Caution: writing to registers which include a status flag 3. Caution: debug-related matters 4. How to Use This Document Main terminology: This table shows main terminology used for FR60. Access size and address position About access size and bit position Meaning of Bit Attribute Symbols Chapter 2 MB91460 Rev.A/Rev.B Overview 2.1 FR60 CPU Core 2.2 Instruction Cache 2.3 Interrupt Controller 2.4 Internal Data RAM 2.5 Internal Instruction/Data RAM 2.6 Embedded Instruction/Data Memory 2.7 External Bus Interface 2.9 Infotainment extension (MB91460 Rev.B) 2.10 Peripheral Function Page Page Page Page 3.MB91460 Series Product Lineup 3. MB91460 Series Product Lineup 20 3.MB91460 Series Product Lineup 21 4.Block Diagram Resource Group 4. Block Diagram IBus Core Group MB91V460 Port Group Page Page 2. I/O Map 25 Table 2-1 I/O Map Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page 6. Pin Definitions Page Page Page Page Page Page Page Page Page Page Page Page Page 94 7. I/O Circuit Type Page 96 8. Pin State Table Page Page Page Page Page Page Page Page Chapter 4 CPU Architecture This chapter describes the architecture of FR60 family CPU. Features of internal architecture 3. CPU 4. 32-bit/16-bit Bus Converter 5. Harvard/Princeton Bus Converter 6. Instruction Overview Arithmetic Operation Load and Store Branch Logical Operation and Bit Operation 7. Data Structure Figure 7-2 Bit Structure of Byte Ordering FR60 has two data allocations as follows. Bit Ordering Figure 7-1 Bit Structure of Bit Ordering 8. Word Alignment Program Access Data Access 9. Addressing Map Direct Addressing Area Page Chapter 5 CPU Registers 1. General-purpose Registers 2. Dedicated Registers [Initial value] 114 2.1 PC: Program Counter Initial value Figure 2-2 Bit Structure of Program Counter (PC) 2.2 PS: Program Status Register Figure 2-3 Bit Structure of Program Status (PS) SCR: System Condition Code Register Figure 2-5 Structure of System Condition Code Register (SCR) SCR [Bit 10, 9] D1 and D0: Step division flag [Bit 8] T: Step trace trap flag ILM: Interrupt Level Mask Register 20 19 18 17 16 [Initial value] ILM4 01111 ILM3 ILM2 ILM1 ILM0 Caution: PS Register 2.3 TBR: Table-base Register 2.4 RP: Return Pointer 2.5 SSP: System Stack Pointer 2.6 USP: User Stack Pointer 31 [Initial value] USP 00000000 0 2.7 MDH, MDL: Multiply & Divide Register At the executing multiplication At the executing division 31 0 MDH MDL Chapter 6 EIT: Exceptions, Interrupts and Traps 3. EIT Trigger 4. Return from EIT 5. EIT Interrupt Level 6. EIT Vector Table 7. Multiple EIT Processing Priority Level of Receipt of EIT Triggers How to Mask Other Triggers upon the Receipt 124 Chapter 6 EIT: Exceptions, Interrupts and Traps 7.Multiple EIT Processing Figure 7-1 Multiple EITs Process 8. Operation 8.1 User Interrupt operation How to determine whether to receive interrupt request or not 8.2 Operation of INT Instruction 8.3 Operation of INTE Instruction 8.4 Operation of Step Trace Trap Condition for detecting step trace trap 8.5 Operation of Undened-instruction Exception Condition for detecting undefined-instruction exception 8.6 Coprocessor Absent Trap 8.7 Coprocessor Error Trap 8.8 Operation of RETI Instruction 9. Caution Chapter 7 Branch Instruction 2. Operation of Branch Instruction with Delay Slot 3. Actual Example (with Delay Slot) 3.1 JMP:D @Ri / CALL:D @Ri Instruction 3.2 RET:D Instruction 3.3 Bcc:D rel Instruction 3.4 CALL:D Instruction Page 5. Branch Instruction without Delay Slot 6. Operation of Branch Instruction without Delay Slot Chapter 8 Device State Transition Device state Standby mode (Low-power-consumption mode) Status transition 134 3. State Transition Diagram This section describes state transition. Figure 3-1 State Transition of MB91460 Series Main clock mode Priority of transition request 3.1 RUN (Normal Operation) 3.2 SLEEP 3.3 STOP 3.4 Oscillation-stabilization-wait RUN 3.5 Oscillation-stabilization-wait Reset 3.6 Operation-initialization Reset (RST) 3.7 Setting-initialization Reset (INIT) 3.8 Priority of Each Request of State Transition Page Page Chapter 9 Reset RUN Software reset instruction Power ON INIT pin input Watchdog timeout From any state 140 Chapter 9 Reset RSRR/STCR State transition control circuit (reset related) State transition control circuit 4.1 RSRR: Reset Cause Register 142 Bit2: Low voltage reset occurred flag Bit1-0: Watchdog period selection 4.2 STCR: Standby Control Register 4.3 MOD: Mode Pins 4.4 Mode Vector 4.5 Reset Vector 145 Initial value to load into PC. 4.6 Device Mode Overview Remarks: On the MB91460 series the ROM area is from 0x0004:0000 up to 0xFFFF:FFFF 000FFFF8 000FFFFC Page 5.6 Reset Cancellation Sequence Page Page 8. Reset Operation Modes 8.1 Normal (Asynchronous) Reset Mode 8.2 Synchronous Reset Operation 9. MCU Operation Mode 9.1 Bus Modes and Access Modes Bus mode Single chip mode Internal ROM, external bus mode 10. Caution Page Page Chapter 10 Standby Sleep mode Stop mode 156 Chapter 10 Standby Standby control State transition control circuit State transition control circuit (for standby modes) 4.1 STCR: Standby Control Register 4.2 TBCR: Timebase timer control register 5.1 Sleep Mode Entering sleep mode Device state in sleep mode Recovery and other items 5.2 Stop mode Entering stop mode Device state in stop mode Recovery and other items 7.1 How do I change to sleep mode? 7.2 How do I change to stop mode? 7.3 How do I set pins to high impedance (Hi-z) during stop mode? 7.4 How do I halt the main clock oscillation during stop mode? 7.5 How do I recover from sleep mode? 7.6 How do I recover from stop mode? Page Page Page Chapter 11 Memory Controller 2. FLASH Interface 3. General Purpose RAM 4. Instruction Cache and Data Buffer 5. Prefetch 7. Registers List of FLASH-IF Registers 8. Explanations of Registers FLASH Interface Control Register Page Page Page Page Page FLASH Memory Wait Timing Register (FMWT) Page Page FLASH Memory Adddress Check register (FMAC) Non-cacheable area definition Chapter 12 Instruction Cache 2. Main body structure Page Control register structure Page Page Page 3. Operating mode conditions Cache status in various operating modes Cache Entry Update 4. Cacheable areas in the instruction cache 5. Settings for handling the I-Cache Page Page Chapter 13 Clock Control Source oscillation Base clock (F): Selectable from 3 different clocks Operating clocks: Selectable from 16 different speeds 190 Chapter 13 Clock Control Selector PLL 4.1 CLKR: Clock Source Control Register Page 4.2 DIV0R: Clock Division Setting Register 0 Page 4.3 DIV1R: Clock Division Setting Register 1 4.4 CSCFG: Clock Source Conguration Register Page 4.5 OSCCR: Oscillation Control Register 199 Chapter 13 Clock Control This section describes how to setup and switch between clocks. 5.1 Clock Setup Sequence (Example) 5.2 Halting and Restarting the Main Clock Oscillation During Subclock Mode (Example) 5.3 Notes Main PLL control Main PLL multiplier Clock division Page 7.1 How do I enable or disable clock operation? 7.2 How do I select the main PLL multiplier ratio? 7.3 How do I select the operating clock source? 203 7.4 How do I set the operation clock division ratios? CPU clock setting Peripheral clock setting Setting for the external bus clock 7.5 How do I halt the main clock in sub clock mode? 7.6 How do I halt the sub clock in sub clock on RC oscillator mode? 7.7 How do I halt the sub clock in main clock mode? Page Page Chapter 14 PLL Interface 3. Frequency calculation 4.1 PLL Control Registers Page Page Page 5. Recommended Settings 6. Clock Auto Gear Up/Down duration mul t k i k1+() = Page 7. Caution Page Chapter 15 CAN Clock Prescaler 3.1 CAN Clock Control Register 219 Bit7-6: Reserved bitAlways write 0 to these register bits. Bit5-0: CAN clock disable Page Chapter 16 Clock Supervisor 222 Chapter 16 Clock Supervisor 2.Clock Supervisor Register 0004AD SSVE SRST Clock Supervisor Control Register (CSVCR) 76543210 R/W R R R/W R/W R/W R/W Initial Value Page 224 Chapter 16 Clock Supervisor 3.Block Diagram Clock Supervisor Timeout Counter Block Diagram Clock Supervisor Clock Supervisor Main Clock Supervisor Sub-Clock Supervisor Control Logic 4. Operation Modes This section describes all operation modes of the Clock Supervisor. Operation mode with initial settings Page Page Page Page Page Disabling the RC-oscillator and the clock supervisors Re-enabling the RC-oscillator and the clock supervisors Sub-clock modes Main Sub Main Main Main Sub Main Stop mode Main Stop Main Operation with single clock device Main Sub Check if reset was asserted by the Clock Supervisor Chapter 17 Clock Modulator Modulation degree and frequency resolution in frequency modulation mode 240 Chapter 17 Clock Modulator 2.Clock Modulator Registers CMCR Clock modulator registers Figure 2-1 Clock modulator registers Address: CMPRL (lower) CMPRH (upper) Clock Modulator Control Register (CMCR) CMCR Clock modulator control register contents Page Clock Modulation Parameter Register (CMPR) Modulation parameter register contents CMPRL (lower) CMPRH (upper) Page Page 3. Application Note Recommended startup sequence for frequency modulation mode Modulation parameter for frequency modulation mode Recommended settings Chapter 18 Timebase Counter 2.1 Timebase Counter (when used to generate the oscillation stabilization wait) 2.2 Events that Invoke an Oscillation Stabilization Wait Wait time after recovering from stop mode: Invoked automatically (timebase counter) When recovering from abnormal state with main PLL selected Time-base counter (when used to generate the oscillation stabilization wait) - INIT pin input - Watchdog reset - STOP Edge detection 4.1 STCR: Standby Control Register 4.2 CLKR: Clock Source Control Register 253 5.1 INIT Pin Input INIT Pin input when main clock running 254 5.2 Watchdog Reset (The specied oscillation stabilization wait time is generated automatically) 255 Chapter 18 Timebase Counter Watchdog reset when main clock operating 5.3 Recovering from Stop Mode via an Interrupt When changing to stop mode without halting the clock oscillation circuit (main PLL/main/ sub): 5.4 The lock wait time for the main PLL must be generated by software. Wait time after main PLL operation enabled: Wait time after main PLL multiplier modified: When main clock continues to run during subclock mode: When main clock halts during subclock mode: 5.7 Types of Oscillation Stabilization Wait Page Page 7.1 How do I setup the oscillation stabilization wait time that is generated automatically? 261 7.2 How do I set the oscillation stabilization wait time without generating it automatically? The settings described below for various cases are required. 7.3 What is the clear timing for the timebase counter? Page Chapter 19 Timebase Timer Timebase timer (TBT) 264 Chapter 19 Timebase Timer 2 24 225 2 2 1 2 2 23 2 4 210 211 2 12 213 2 14 2 15 2 16 2 17 2 18 2 19 2 20 221 2 22 2 Selector 4.1 TBCR: Timebase Timer Control Register 4.2 CTBR: Timebase Counter Clear Register 267 Chapter 19 Timebase Timer Timebase timer operation is described. 5.1 Timebase Timer Interrupt Example (Main PLL Lock Wait) Page 7.2 What Is the count clock of the timebase counter? 7.3 How to operate the timebase timer? 7.4 How is the timebase timer (=timebase counter) operation stopped? 7.5 How is the timebase counter (=timebase timer) cleared? 7.6 How about the interrupt-associated registers? 7.7 What are the interrupt types? 7.8 How is an interrupt enabled? Page Page Chapter 20 Software Watchdog Timer Watchdog timer Chapter 20 Software Watchdog Timer Selector Edge detection -Sleep -Stop -Oscillation stability wait RUN 4.1 RSRR: Watchdog Timer Control Register 276 Bit2: Low voltage reset occurred flag Bit1-0: Watchdog interval time selection 4.2 WPR: Watchdog Reset Generation Postponement Register 4.3 CTBR: Timebase Counter Clear Register 278 This section describes the watchdog operation. 5.1 Watchdog (Detecting Runaway) 5.2 Starting the Watchdog Timer and Setting the Watchdog Timer Period 5.3 Postponing the Generation of a Watchdog Reset 5.4 Conrming that the Watchdog Reset has been Generated 5.5 Temporarily Stopped Watchdog Timer (Automatic Generation Postponement) 5.6 Stopping the Watchdog Timer Page 7.1 What are the types of watchdog interval time and how are they selected? 7.2 How is the watchdog operation started (set to valid)? 7.3 How can we check that the watchdog reset has been generated? 7.4 How is the watchdog stopped? 7.5 How do I clear the watchdog timer (1-bit counter)? Page Chapter 21 Hardware Watchdog Timer Hardware watchdog timer 2. Configuration Block diagram of the hardware watchdog timer 3. Register 3.1 Hardware watchdog timer control and status register 3.2 Hardware watchdog timer duration register 4. Functions Function of the hardware watchdog timer Period of the hardware watchdog timer 5. Caution Chapter 22 Main Oscillation Stabilisation Timer 290 Chapter 22 Main Oscillation Stabilisation Timer 22 22222 Main clock oscillation stability wait timer Setting disable F / F Edge detection 4. Register 4.1 OSCRH: Control Register for the Main Clock Oscillation Stability Wait Timer 292 This section describes the main clock oscillation stability wait timer operation. 5.1 Main Clock Oscillation Stability Wait 5.2 Interval Interrupt Page 7.1 What are the types of interval time (wait time) and how are they selected? 7.2 How do I select the count clock? 7.3 How is the main clock oscillation stability wait timer count operation enabled/ disabled? 7.4 How is the main clock oscillation stability wait timer cleared? 7.5 What happens with the interrupt-associated registers? Page Page Page Chapter 23 Sub Oscillation Stabilisation Timer 300 Chapter 23 Sub Oscillation Stabilisation Timer Edge detection Selector Clock timer Clock timer (14-bit free run timer) 01234567891011121314 Clock timer Interrupt (#49) 4.1 WPCRH: Sub oscillation stabilisation timer Control Register Page 303 5.1 Subclock Oscillation Stability Wait Interrupt Figure 5-1 Reference 5.2 Interval Interrupt (Clock Interrupt) 5.3 Returning from the Stop Mode due to Interval Operation (Clock Interrupt) Page 7.1 What are the types of interval time (wait time) and how are they selected? 7.2 How is the count clock selected? 7.3 How is the sub oscillation stabilisation timer cleared? 7.4 What are interrupt-associated registers? 7.5 What are the types of interrupt? 7.6 How is the interrupt enabled? 7.7 How is the sub oscillation stabilisation timer stopped counting? Page Page Chapter 24 Interrupt Control Chapter 24 Interrupt Control Priority judging circuit Rewrite Address I flag 0 1 SSP RAM PS, PC) 4.1 ICR: Interrupt Control Register The register that specifies the interrupt level of an interrupt request. Page Page Page 317 4.2 Interrupt Vector 318 Chapter 24 Interrupt Control The following section explains priority determination operation of interrupt control. Priority determination 7.1 How can I set interrupt levels? 7.2 How do I enable interrupts? 7.3 How do I disable interrupts? Page Chapter 25 External Interrupt Chapter 25 External Interrupt External interrupts 0 - 7 Edge detection circuit H L Register number External interrupts 8 - 15 Register number Port function Page 4.1 ELVR: Interrupt Request Level Register 4.2 EIRR: Interrupt Request Register 4.3 ENIR: Interrupt Request Enable Register Page 7.1 What are the types and setting procedures of detect levels? 7.2 How do I set INT pin as the input? 329 7.3 What interrupt registers are used? Interrupt causes are limited to external interrupts. There is no bit for selection. 7.4 Interrupt types 7.5 How do I enable, disable, and clear interrupts? Page Page Chapter 26 DMA Controller Hardware Configuration Main Functions Transfer mode 334 Block Diagram DMA Controller (DMAC) registers Notes on Setting Registers Bit Configuration of Control/Status Registers A (DMACA0 to 4) Detailed Bit of Control/Status Registers A (DMACA0 to 4) Page Page Page 340 Table 2-2 Settings for Extended Transfer Request Sources 341 Table 2-2 Settings for Extended Transfer Request Sources Page Bit Configuration of Control/Status Register B (DMACB0 to 4) Detailed Bit of Control/Status Register B (DMACB0 to 4) Page Page Page Page Page Page Page Bit Configuration of DMAC All-Channel Control Register (DMACR) Detailed Bit of DMAC All-Channel Control Register (DMACR) Page Page Page Fly-by transfer (I/O --> memory) Transfer Address Specifying the address for a 2-cycle transfer Specifying the address for a fly-by transfer Transfer Count and Transfer End Transfer count Software requests can always be used regardless of the settings of other requests. External Transfer Request Pin Edge detection Level detection Built-in Peripheral Request Selection of the Transfer Sequence Burst 2-cycle transfer Burst fly-by transfer Demand Transfer 2-Cycle Transfer Demand transfer fly-by transfer Step/block transfer 2-cycle transfer Step/block transfer fly-by transfer Block Size Reload Operation Transfer count register reloading Transfer source address register reloading Transfer destination address register reloading Special examples of operating mode and the reload operation Address Register Specifications Features of the Address Register Function of the Address Register Data Length (Data width) Transfer Count Control Reload Operation DMA Transfer and Interrupts Suppressing DMA Page Clearing Peripheral Interrupts by DMA Temporary Stopping NMI/hold suppress level interrupt processing Operation End/Stopping Transfer end Disabling all channels Stopping Due To an Error Transfer stop requests from peripheral circuits Occurrence of an Address Error DMAC Interrupt Control DMA Transfer during Sleep Priority Among Channels Fixed mode Rotation mode (ch.0 to ch.1 only) Channel Group Minimum Effective Pulse Width of the DREQ pin Input Negate Timing of the DREQ Pin Input when a Demand Transfer Request is Stopped For 2-cycle transfer For fly-by (read/write) transfer Page Page Block Transfer Burst Transfer Demand Transfer Page 5. Data Bus This section shows the flow of data during 2-cycle transfer and fly-by transfer. Flow of Data During 2-Cycle Transfer Flow of Data During Fly-By Transfer Page DMA External Interface Pins Timing of Transfer Other Than Demand Transfer Timing of Demand Transfer Transfer Mode Settings 2-cycle transfer mode Fly-by transfer mode Page Chapter 27 Delayed Interrupt Delay interrupt 4.1 DICR: 7.1 What are interrupt-associated registers? 7.2 How is the interrupt request generated/cleared? Page Chapter 28 Bit Search Chapter 28 Bit Search BSRR Bit search BSD0/ BSD1/ BS DC Detection result BSRR 0-/1-/Changing-position-detection data register Bit search Detection circuit (0-/1-/Changing-positions) Detection data (BSD1) Page 4.2 BSRR: Detection Result Register 5.1 Zero detection 5.2 One Detection Data 12H(18Decimal) Bit position from MSB Scan Detection result 5.3 Changing Position Detection Data Table 5-1 The Relationship Between the Bit Position and the Value to be Returned (Decimal Notation) Bit position from MSB Scan Detection result Page Page Page Page Chapter 29 MPU / EDSU Page 3. Break Functions 3.1 Instruction address break 3.2 Operand address break Page 3.3 Data value break 3.4 Using operand with data break 3.5 Memory Protection 3.6 Break Factors Page 4.1 List of EDSU Registers Page Page 4.2 Explanations of Registers EDSU Control Register (BCTRL) Page Page Page EDSU Status Register (BSTAT) Page Page EDSU Instruction Address Capture Register (BIAC) EDSU Operand Address Capture Register (BOAC) EDSU Break Detection Interrupt Request Register (BIRQ) Page EDSU Channel Configuration Register (BCR0...BCR7) Page Page Page Page Page Page Page Break Address/Data register (BAD0...BAD31) Page 429 Chapter 29 MPU / EDSU 5.Quick Reference Figure 5-1 Register Quick Reference 5. Quick Reference 430 Chapter 29 MPU / EDSU 5.Quick Reference Figure 5-2 Comparator Group Structure (drawn for two groups) CTCCTC Break Detection Evaluation Chapter 30 I/O Ports 1. I/O Ports Functions For enabling the resource functions, please refer to section ........ Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page 453 2. I/O Circuit Types 2.1 I/O Cell List MB91V460 There are various types of input stages. The following table lists the input voltages VIL / VIH. 2.2 I/O Input Voltages (VIL/VIH) 3. Port Register Settings 3.1 General Rules For all ports, the following rules are valid: Page 3.2 I/O Port Block Diagram 3.3 Port Input Enable This section describes the Port Input Enable function. PORTEN: Port Input Enable. 3.4 Port Function Register Setup This section describes the Port Function Registers of each port. P00: The functions of Port 00 are controlled by PFR00 P01: The functions of Port 01 are controlled by PFR01 P02: The functions of Port 02 are controlled by PFR02 P03: The functions of Port 03 are controlled by PFR03 P04: The functions of Port 04 are controlled by PFR04 P05: The functions of Port 05 are controlled by PFR05 P06: The functions of Port 06 are controlled by PFR06 P07: The functions of Port 07 are controlled by PFR07 P08: The functions of Port 08 are controlled by PFR08 P09: The functions of Port 09 are controlled by PFR09 P10: The functions of Port 10 are controlled by PFR10 and EPFR10 P11: The functions of Port 11 are controlled by PFR11 P12: The functions of Port 12 are controlled by PFR12 and EPFR12 P13: The functions of Port 13 are controlled by PFR13 and EPFR13 P14: The functions of Port 14 are controlled by PFR14 and EPFR14 Page P15: The functions of Port 15 are controlled by PFR15 and EPFR15 P16: The functions of Port 16 are controlled by PFR16 and EPFR16 P17: The functions of Port 17 are controlled by PFR17 P18: The functions of Port 18 are controlled by PFR18 and EPFR18 P19: The functions of Port 19 are controlled by PFR19 and EPFR19 P20: The functions of Port 20 are controlled by PFR20 and EPFR20 P21: The functions of Port 21 are controlled by PFR21 and EPFR21 P22: The functions of Port 22 are controlled by PFR22 Page P23: The functions of Port 23 are controlled by PFR23 Page P24: The functions of Port 24 are controlled by PFR24 Page P25: The functions of Port 25 are controlled by PFR25 P26: The functions of Port 26 are controlled by PFR26 and EPFR26 P27: The functions of Port 27 are controlled by PFR27 and EPFR27 P28: The functions of Port 28 are controlled by PFR28 P29: The functions of Port 29 are controlled by PFR29 P30: The functions of Port 30 are controlled by PFR30 P31: The functions of Port 31 are controlled by PFR31 P32: The functions of Port 32 are controlled by PFR32 and EPFR32 P33: The functions of Port 33 are controlled by PFR33 and EPFR33 P34: The functions of Port 34 are controlled by PFR34 and EPFR34 P35: The functions of Port 35 are controlled by PFR35 and EPFR35 3.5 Port Input Level Selection Page 3.6 Programmable Pull-Up/Pull Down Resistors Page 502 3.7 Programmable Port Output Drive Page Page Page Chapter 31 External Bus The external bus interface has the following features: In each chip select area, the following functions can be set independently: A different detailed timing can be set for each access timing type. Page 509 1.2 Block Diagram Figure 1-1 Block Diagram of the External Bus Interface 1.3 I/O Pins Ordinary bus interface Memory interface DMA interface 1.4 Register List Page Page Functions of Bits in the Area Select Registers (ASR0-7) Configuration of Area Configuration Registers 0-7 (ACR0-7) Page Page Page Page Page CS area mask setting function 520 2.External Bus Interface Registers Configuration of the Area Wait Registers (AWR0-7) Page Page Page Page Page Memory type A(SDRAM/FCRAM) and Memory type B(FCRAM) Page Page Structure of the Memory Setting Register (MCRA for SDRAM/FCRAM auto - precharge OFF mode) Structure of the Memory Setting Register (MCRB for FCRAM auto - precharge ON mode) Configuration of the I/O Wait Registers for DMAC (IOWR0-3) Functions of Bits in the I/O Wait Registers for DMAC (IOWR0-3) Page Configuration of the Chip Select Enable Register (CSER) Functions of Bits in the Chip Select Enable Register (CSER) Configuration of the Cache Enable Register (CHER) Functions of Bits in the Cache Enable Register (CHER) Configuration of the Pin/Timing Control Register (TCR) Functions of Bits in the Pin/Timing Control Register (TCR) Page Structure of the Refresh Control Register (RCR) Bit Functions of the Refresh Control Register (RCR) Page Page Page Example of Setting the Chip Select Area Example of setting ASRs and ASZ3-0 Relationship between Data Bus Width and Control Signal Ordinary bus interface Time division I/O interface SDRAM Interface Data Format Word access (when LD/ST instruction executed) Data Bus Width External Bus Access 547 Figure 4-10 External bus Access for 32-Bit Bus Width Figure 4-11 External bus Access for 16-Bit Bus Width (A) Word access (B) Halfword access Example of Connection with External Devices (A) Word access (B) Halfword access Differences between Little Endian and Big Endian Word access Halfword access Byte access Restrictions on the Little Endian Area Data Format Data Bus Width Examples of Connection with External Devices Page Page Word Access Halfword Access Page Page Page Page Page Ordinary Bus Interface 5.1 Basic Timing This section shows the basic timing for successive accesses. Basic Timing (For Successive Accesses) Operation Timing of the WRn + Byte Control Type Page 5.3 Read -> Write Operation This section shows the operating timing for read -> write. Operation Timing of Read -> Write 5.4 Write -> Write Operation This section shows the operation timing for write -> write. Write -> Write Operation 5.5 Auto-Wait Cycle This section shows the operation timing for the auto-wait cycle. Auto-Wait Cycle Timing 5.6 External Wait Cycle This section shows the operation timing for the external wait cycle. External Wait Cycle Timing Operation Timing for Synchronous Write Enable Output Page 5.8 CSn Delay Setting This section shows the operation timing for the CSn delay setting. Operation Timing for the CS Delay Setting Operation Timing for the CSn -> RD/WRn Setup andRD/WRn -> CSn Hold Settings Operation Timing for DMA Fly-By Transfer (I/O -> Memory) Operation Timing for DMA Fly-By Transfer (Memory -> I/O) Page Burst Access Operation Page Without External Wait With External Wait CSn -> RD/WRn Setup Page 8. Prefetch Operation This section explains the prefetch operation. Prefetch Operation Basic conditions for starting external access using prefetch Optional clear for temporary stopping of a prefetch access Unit for one prefetch access operation Burst length setting and prefetch efficiency Reading from the prefetch buffer Clearing/updating the prefetch buffer Restrictions on prefetch-enabled areas SDRAM/FCRAM interface Burst Read/Write Operation Timing Single Read/Write Operation Timing Single Read Operation Timing Single Read/Write Operation Timing Auto - refresh Operation Timing 9.1 Self Refresh This section describes self - refreshing. Self Refresh Self - refresh mode transition procedure Self - refresh mode reset procedure 9.2 Power-on Sequence This section describes the power - on sequence. Power-on Sequence Connecting SDRAM/FCRAM to Many Areas 9.4 Address Multiplexing Format This section describes the address multiplexing format. Address Multiplexing Format Page Using 8 - bit SDRAM/FCRAM (Big endian) 589 9.SDRAM/FCRAM Interface Operation Figure 9-7 Using 64 - Mbit SDRAM Using 16 - bit SDRAM/FCRAM SDRAM(No.3) SDRAM(No.4) 590 9.SDRAM/FCRAM Interface Operation Using 32 - bit SDRAM SDRAM(No.3) SDRAM(No.4) Page Page Page 10.2 DMA Fly-By Transfer (Memory -> I/O) This section explains DMA fly-by transfer (memory -> I/O). DMA Fly-By Transfer (Memory -> I/O) Page 596 Figure 10-3 Timing Chart for DMA Fly - by Transfer (I/O to SDRAM/FCRAM) DMA Fly-By Transfer (SDRAM/FCRAM -> I/O) 598 At SDRAM page hit (Shortest) Figure 10-4 Timing Chart for DMA Fly - by Transfer (SDRAM/FCRAM to I/O) with Page Hits (Shortest) At SDRAM page misses Page Page 2-Cycle Transfer (Internal RAM -> External I/O, RAM) 2-Cycle Transfer (External -> I/O) 2-Cycle Transfer (I/O -> External) 605 2-Cycle Transfer (I/O -> SDRAM/FCRAM) Figure 1.10 - 12 shows a timing chart for two - cycle transfer (SDRAM/FCRAM to I/O) 2-Cycle Transfer (SDRAM/FCRAM -> I/O) 606 Figure 10-12 Timing Chart for Two - cycle Transfer (SDRAM/FCRAM to I/O) Page Releasing the Bus Right 1 cycle Read 1 cycle 12. Procedure for Setting a Register This section explains the procedure for setting a register. Procedure for Setting a Register Notes for Use Page Chapter 32 USART (LIN / FIFO) USART Functions USART operation modes USART Interrupts 2. USART Configuration USART consists of the following blocks: 617 2.USART Conguration SSR SSR SCR0 ESCR ECCR Explanation of the different blocks SCK0 SOT0 Page Page 3. USART Pins USART Pins PDR PFR DDR 4. USART Registers 4.1 Serial Control Register 04 (SCR04) 622 Figure 4-1 Serial Control Register 04 (SCR04) 15 14 13 12 11 10 9 8 Initial value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W WR/W R/W R/W Page 624 4.2 Serial Mode Register 04 (SMR04) R/WR/W R/W R/W W W R/WR/W 4.3 Serial Status Register 04 (SSR04) 626 Figure 4-3 Conguration of the Serial Status register 04 (SSR04) 15 14 13 12 11 10 9 8 Initial value 0 0 0 0 1 0 0 0 RRRR R/WR R/WR/W Page 4.4 Reception and Transmission Data Register (RDR04 / TDR04) Reception: Transmission: 629 * see table 4-6 for RMW access! 4.5 Extended Status/Control Register (ESCR04) 15 14 13 12 11 10 9 8 Initial value 0 0 0 0 0 1 0 0 R/WR/W R/W R/W R/WR/W R/WR/W 4.6 Extended Communication Control Register (ECCR04) 631 Figure 4-6 Conguration of the Extended Communication Control Register (ECCR04) Initial value 0 0 0 0 0 0 X X W R/W R/W R/WR/W R R 76543210 R/W 4.7 Baud Rate / Reload Counter Register 0 and 1 (BGR04 / 14) Page 634 4.8 FIFO Control Register (FCR04) Figure 4-8 Configuration of FIFO control registe R/WR/W R/W R/W R/WR R/W R/W Page 636 4.9 FIFO Status Register (FSR04) Figure 4-9 Conguration of FIFO status register RRRR RRRR Page 5. USART Interrupts USART Interrupts Reception Interrupt Transmission Interrupt LIN Synchronization Break Interrupt LIN Synchronization Field Edge Detection Interrupts Bus Idle Interrupt 5.1 Reception Interrupt Generation and Flag Set Timing Reception Interrupt Generation and Flag Set Timing 5.2 Transmission Interrupt Generation and Flag Set Timing Transmission Interrupt Generation and Flag Set Timing Transmission Interrupt Request Generation Timing 6. USART Baud Rates USART Baud Rate Selection 643 6.USART Baud Rates edge detected 6.1 Setting the Baud Rate Calculating the baud rate v = [F / b] - 1 , Example of Calculation clock Suggested Division Ratios for different machine speeds and baud rates Counting Example 6.2 Restarting the Reload Counter Programmable Restart Automatic Restart Operation of USART Inter-CPU Connection Method Synchronization Methods Signal Mode Operation Enable Bit 7.1 Operation in Asynchronous Mode (Op. Modes 0 and 1) Transfer data format Transmission Operation Reception Operation Stop Bit, Error Detection, and Parity 7.2 Operation in Synchronous Mode (Operation Mode 2) Transfer data format (standard synchronous) Transfer data format Clock inversion and start/stop bits in mode 2 Clock Supply Data signal mode Error Detection Communication 7.3 Operation with LIN Function (Operation Mode 3) USART as LIN master USART as LIN slave LIN bus timing 7.4 Direct Access to Serial Pins USART Direct Pin Access 7.5 Bidirectional Communication Function (Normal Mode) Bidirectional Communication Function Inter-CPU Connection 7.6 Master-Slave Communication Function (Multiprocessor Mode) Master-slave Communication Function Inter-CPU Connection Function Selection Communication Procedure 658 Figure 7-12 Master-slave communication owchart 7.7 LIN Communication Function LIN-Master-Slave Communication Function LIN device connection 7.8 Sample Flowcharts for USART in LIN Communication (Operation Mode 3) 660 USART as master device Figure 7-15 USART LIN master ow chart 661 USART as slave device continued next page Figure 7-16 USART LIN slave ow chart (part1) 662 Figure 7-17 USART LIN slave ow chart (part 2) continuation from previous page 8. Notes on using USART Notes on using USART are given below. Baud Rate Detection Using the Input Capture Units Chapter 33 I2C Controller Features Chapter 33 I2C Controller Block Diagram General call Arbitration Loss Detector Slave Address Comparator 667 2. I2C Interface Registers This section describes the function of the I2C interface registers in detail. Ten bit slave address MasK register (ITMK0) Bus Control Register (IBCR0) Bus Status Register (IBSR0) Ten Bit slave Address register (ITBA0) Seven bit slave address MasK register (ISMK0) Seven Bit slave Address register (ISBA0) Clock control register (ICCR0) Data Register (IDAR0) 2.1 Bus Control Register (IBCR0) Page Page Page 2.2 Bus Status Register (IBSR0) Page Page 2.3 Ten Bit Slave Address Register (ITBA0) 2.4 Ten Bit Address Mask Register (ITMK0) Page 2.5 Seven Bit Slave Address Register (ISBA0) 2.6 Seven Bit Slave Address Mask Register (ISMK0) 2.7 Data Register (IDAR0) 2.8 Clock Control Register (ICCR0) Prescaler settings: SCL Waveforms Data sending 3. I2C Interface Operation Start Conditions Stop Conditions Slave Address Detection Slave Address Masking Addressing Slaves Arbitration Acknowledgement 4. Programming Flow Charts Example Of Slave Addressing And Sending Data Transfer End Y Enable Interface EN:=1; Example Of Receiving Data Y Example Of An Interrupt Handler Page Chapter 34 CAN Controller The CAN implements the following features: This chapter uses the following terms and abbreviations. 2. Register Description 2.1 Programmers Model Page Page 695 Figure 2-1 CAN Register Summary After hardware reset, the registers of the CAN hold the values described in Figure 2-1. Figure 2-2 CAN Prescaler Register Summary 2.2 Hardware Reset Description Address Register Note 2.3 CAN Protocol Related Registers CAN Control Register (CTRLR) Page Status Register (STATR) Function of the Status Register (STATR) Status Interrupts Error Counter (ERRCNT) Bit Timing Register (BTR) Function of the Bit Timing Register (BTR) Test Register (TESTR) Function of the Test Register (TESTR) BRP Extension Register (BRPER) Function of the BRP Extension Register (BRPER) 2.4 Message Interface Register Sets 705 Figure 2-3 IF1 and IF2 Message Interface Register Sets IFx Command Request Registers (IFxCREQ) Function of the IFx Command Request Registers (IFxCREQ) IFx Command Mask Register (IFxCMSK) Function of the IFx Command Mask Register (IFxCMSK) IFx Mask Registers (IFxMSK) 709 IFx Arbitration Registers (IFxARB) The bits of the Message Buffer registers mirror the Message Objects in the Message RAM. 710 IFx Message Control Register (IFxMCTR) IFx Data A and Data B Registers (IFxDTA, IFxDTB) 2.5 Message Object in the Message Memory Page Page 2.6 Message Handler Registers Interrupt Register (INTR) Function of the Interrupt Register (INTR) Page 716 Table 2-1 Additional ags when more than 32 message buffers exist New Data Registers (NEWDT) 717 Interrupt Pending Registers (INTPND) Table 2-2 Additional ags when more than 32 message buffers exist 718 Message Valid Registers (MSGVAL) Table 2-3 Additional ags when more than 32 message buffers exist 1 This message object is the source of an interrupt. Page 3. Functional Description 3.1 Software Initialisation 3.2 CAN Message Transfer 3.3 Disabled Automatic Retransmission 3.4 Test Mode 3.5 Silent Mode 3.6 Loop Back Mode 3.7 Loop Back combined with Silent Mode 3.8 Basic Mode 3.9 Software control of Pin CAN_TX 4. CAN Application 4.1 Management of Message Objects 4.2 Message Handler State Machine 4.3 Data Transfer from/to Message RAM 4.4 Transmission of Messages 4.5 Acceptance Filtering of Received Messages 4.6 Reception of Data Frame 4.7 Reception of Remote Frame 4.8 Receive / Transmit Priority 4.9 Conguration of a Transmit Object 4.10 Updating a Transmit Object 4.11 Conguration of a Receive Object 4.12 Handling of Received Messages 4.13 Conguration of a FIFO Buffer 4.14 Reception of Messages with FIFO Buffers 4.15 Reading from a FIFO Buffer 4.16 Handling of Interrupts 4.17 Bit Time and Bit Rate Page Page Chapter 35 Free-Run Timer 734 3.Conguration Diagram Output compare Timer data register 3. Configuration Diagram Free-run Timer 0 1 TCDT Free-run Timer interrupt 4.1 TCCS: Timer Control Register Page Page 4.2 TCDT: Timer Data Register 5.1 Count Operation of the Free-run Timer 5.2 Various Clear Operations of the Free-run Timer Page 742 7.1 What are the types of the internal clock, and how do I select? Set with count operation bits (TCCS.STOP). 7.2 How do I select the external clock? Set with clock selection bits (TCCS.ECLK), data direction bits, and (extra) port function bits. 7.3 How do I enable / disable the count operation of the free-run timer? 7.4 How do I clear the free-run timer? 7.5 What interrupt registers are used? 7.6 Interrupt Types 7.7 How do I enable interrupts? 7.8 How do I stop the free-run timer? 7.9 How are the free-run timer assigned to ICU and OCU? Page Page Chapter 36 Input Capture Chapter 36 Input Capture Input capture 0-1 IPCP1 (CP15-CP0) Capture data register 1 ICU0 / P14.0 Free-run timer 0 4.1 IPCP: Input Capture Data Register 4.2 ICS: Input Capture Control Register Page 752 The input capture operation is described below. 5.1 Capture Timing, Interrupt Timing 753 5.2 Input Capture Edge Specication and Operation When specifying rising edge When specifying falling edge Both edges Page 7.1 What are the varieties of active edge polarity for external input, and how do I select them? 7.2 What about setting the external input pins (ICU0-7)? 7.3 What about interrupt-related registers? 7.4 What are the types of interrupts? 7.5 How do I enable interrupts? 7.6 How do I measure the pulse width of the input signal? Page Chapter 37 Output Compare 760 Chapter 37 Output Compare 3.Conguration Diagram Latch General-use port read 3. Configuration Diagram Figure 3-1 Conguration Diagram Output Compare 0-1 OCU0 Interrupt (#100) From general-use port register 4.1 OCS: Output Control Register Page Page 4.2 OCCP: Compare Register Chapter 37 Output Compare 5.1 Output Compare Output (Independent Reversal) CMODE=0 5.2 Output Compare Output (Cooperative Reversal) CMODE=1 767 Table 6-1 Settings Necessary for Using Output Compare Table 6-2 Item Necessary to Clear the Free-run Timer upon Compare-match. Table 6-3 Item Necessary for Performing Interrupts 768 7.1 How do I set the compare value? Write the compare value to compare registers OCCP0 - OCCP7. 7.2 How do I set the compare mode? (for OCU1, OCU3, OCU5, OCU7 output) This is done using compare mode bits (OCS01.CMOD), (OCS23.CMOD), (OCS45.CMOD), (OCS67.CMOD). 7.3 How do I enable/disable the compare operation? 7.4 How do I set the initial level of the compare pin output? 7.5 How do I set the output for compare pins OCU0-OCU7? 7.6 How do I clear the free-run timer? 7.7 How do I enable the compare operation? 7.9 What are the interrupt-related registers? 771 7.10 What are the types of interrupts? 7.11 How do I enable interrupts? 7.12 Compare value calculation procedure Page Page Chapter 38 Reload Timer 776 Chapter 38 Reload Timer TMR0 0 Reload Timer 0 (Internal clock count) Reload/activation/stop control circuit Timer interrupt (underflow) 777 Chapter 38 Reload Timer Reload timer 0 (External event count) Reload/activation/stop control circuit 4.1 TMCSR: Reload Timer Control Status Register Page Page 4.2 TMR: Timer Register 4.3 TMRLR: Reload register 5.1 Internal Clock/Reload Mode 5.2 Internal Clock/One-shot Mode 5.3 External Event Clock Reload Mode 5.4 External Event Clock/One-shot Mode 5.5 Operation during Reset 5.6 Operation during Sleep Mode 5.7 Operation during Stop Mode 5.8 Operation when Returning from Stop Mode 5.9 Status Transition 787 Table 6-1 Settings Necessary for Moving the Reload Timer (Internal Clock Operation) Table 6-2 Settings Necessary for Moving the Reload Timer (External Event Operation) Page 7.1 What is the reload value setting (rewriting) procedure? 7.2 What are the kinds of count clocks and how are they selected? 7.3 How to I enable/disable the reload timer count operation? 7.4 How do I set the reload timer mode (reload/one-shot)? 7.5 How do I reverse the output level? Page 7.6 What are the kinds of triggers, and how do I select them? 7.7 What are the types of external event clock active edges and how do I select them? 7.8 How do I make a pin a TOT output pin? 7.9 How do I make the TIN pin into an external event input pin, or an external trigger input pin? 7.10 How do I generate an activation trigger? 7.11 What are the interrupt-related registers? 7.12 How do I enable interrupts? 7.13 How do I stop the reload timer? Page Chapter 39 Programmable Pulse Generator L H L L H H L H H L L H L H L H Page Chapter 39 Programmable Pulse Generator PPG (0-3) Selector PCSR PDUT PTMR Selector Page 4.1 PCSR: PPG Cycle Setting Register 4.2 PDUT: PPG Duty Setting Register 4.3 PCN: PPG Control Status register Page Page 4.4 GCN1: General Control register 1 Page 4.5 GCN2: General Control Register 2 4.6 PTMR: PPG Timer Register 808 (See 8. Caution (Page No.821).) 5.1 PWM Operation In PWM operation, variable-duty pulses are generated from the PPG pin. 809 Equation 5.2 One-Shot Operation In one-shot operation, one-shot pulses are generated from the PPG pin. 5.3 Restart Operation Page Page 7.1 How do I set (rewrite) a cycle and a duty? 7.2 How do I enable or disable PPG operations? 7.3 How do I set the PPG operation mode (PWM operation/one-shot operation)? 7.4 How do I get it restarted? 7.5 What count clocks are available and how are they selected? 7.6 How do I clamp the PPG pin output level? 7.7 What activation triggers are available and how are they selected? 816 Triggers are selectable for PPG8, PPG9, PPG10, and PPG11 independently. Triggers are selectable for PPG12, PPG13, PPG14, and PPG15 independently. 7.8 How do I invert the output polarity? 7.9 How do I program a pin as a PPG output pin? 7.10 How do I generate an activation trigger? 7.11 How do I stop a PPG operation? 7.12 What interrupt registers are used? Page 7.13 What interrupts are available and how are they selected? 7.14 How do I enable, disable and clear interrupts? Page Page Chapter 40 Pulse Frequency Modulator 16-bit Reload Counter 0 Register Configuration 16-bit Reload Counter 1 Register Configuration 825 Chapter 40 Pulse Frequency Modulator 1.PFM Overview Figure 1-2 Block Diagram of the 16-bit Pulse Frequency Modulator Block Diagram of the 16-Bit Pulse Frequency Modulator Control Status Register (P0TMCSR, P1TMCSR) P0TMCSR, P1TMCSR structure Functions of the P0TMCSR, P1TMCSR bits Page 16-bit Counter Register (P0TMR, P1TMR) P0TMR, P1TMR structure 16-bit Reload Register (P0TMRLR, P1TMRLR) P0TMRLR, P1TMRLR structure Internal Clock Operation Counter activation and operation timing Underflow Operation Underflow operation timing Counter Operation States 832 Chapter 40 Pulse Frequency Modulator 3.Reload Counter Operation Figure 3-3 Counter State Transitions Counter state transitions 4. PFM Operation and Setting Page Chapter 41 Up/Down Counter 2. Feature UDCR0 8 bit mode Reload Up/Down Counter 0 (8 Bit Mode) BIN0/SOT2/P20.1 ZIN0/SCK2/P20.2 0 8 bit mode Up/Down Counter 1 (8 Bit Mode) BIN1/SOT3/P20.5 ZIN1/SCK3/P20.6 0 8 bit mode 838 Figure 3-3 Conguration Diagram Counter clear AIN0/SIN2/P20.0 ZIN0/SCK2/P20.2 Page 4.1 UDCC: Counter Control Register Page Page 4.2 UDCS: Count Status Register Page 4.3 UDCR: Up/Down Counter Register 16 Bit Mode (M16E= 1) 8 Bit Mode (M16E=0) 4.4 UDRC: Up/Down Reload/Compare Register 16 Bit Mode (M16E=1) 8 Bit Mode (M16E=0) Page 5.1 Timer Mode CMS[1:0]=00 5.2 Up/Down Count Mode CMS[1:0]=01 5.3 Up/Down Count Mode CMS[1:0]=01 5.4 Phase Difference Count Mode (Multiply by 2) CMS[1:0]=10 AIN BIN 5.5 Phase Difference Count Mode (Multiply by 4) CMS[1:0]=11 AIN BIN 853 5.6 Clear Timing 5.7 Reload Timing 5.8 Writing a Value to Counter RCR CSTR CTUT XXH 67H 67H 855 Table 6-1 Required Settings to Run Up/Down Counter in Timer Mode Table 6-2 Required Settings to Run Up/Down Counter in Up/Down Count Mode 856 Table 6-4 Required Settings for Up/Down Counter Interrupt Table 6-5 Required Settings to Deactivate Up/Down Counter Page 7.8 How do I clear Up/Down Counter? 7.9 How do I clear Up/Down Counter using the ZIN pin? 7.10 How do I control Up/Down Counter's count operation using the ZIN pin? 7.11 How do I enable/disable Up/Down Counter's count operation? 7.12 How do I know the previous count direction (the current rotation direction)? 7.13 How do I know count direction changes? 7.14 How do I know that a compare-match has occurred? 7.15 How do I know that an overow or underow has occurred? 7.16 How do I set the reload/compare value? 7.17 What are interrupt-related registers? 7.18 What interrupts are available and how are they selected? 7.19 How do I enable (select), disable or clear interrupts? Page Chapter 42 Sound Generator Page Chapter 42 Sound Generator 3.Registers 3.1 Register Details Sound Control Register (SGCR) Frequency Data Register (SGFR) Amplitude Data Register (SAGR) Decrement Grade Register (SGDR) Tone Count Register (SGTR) Page Page 871 Chapter 43 Stepper Motor Controller SMC channel 0 (ADC input) PWM2M Remark: The SMC channels 0, 1, 2 and 3 are shared with ADC inputs. Block Diagram of Stepping Motor Controller Remark: The SMC channels 4 and 5 are not shared with ADC inputs. 2. Registers CK EN PWM PWM1P PWM1M PWM2P CK EN PWM 2.1 Registers for Stepping Motor Controller PWM Control Register P2 0x0C1, 0x0C3 0x0C5, 0x0C7 0x0C9, 0x0CB Page PWM1&2 Compare Registers 877 Figure 2-1 Relationship between the Compare Register Setting Value and PWM Pulse Width PWM1&2 Selection Registers 0x096, 0x09E 0x0A6, 0x0AE 0x0B6, 0x0BE 0x097, 0x09F 0x0A7, 0x0AF 0x0B7, 0x0BF 879 2.Registers When set a BS bit in "0" before the PWM cycle end Load Not load XXXh Page 881 3. Operation The operation of the stepping motor controller is explained. Setting Operation of Stepping Motor Controller Figure 3-1 Setting of Stepping Motor Controller Operation of PWM-pulse generator Selection of motor drive signals Page Page Chapter 44 A/D Converter 1. Overview of A/D Converter Input impedance 886 Chapter 44 A/D Converter 2.Block Diagram of A/D Converter 2. Block Diagram of A/D Converter Following figure shows block diagram of A/D converter. Block diagram of A/D converter input circ u it Sample &Hold circuit Comparator 3. Registers of A/D Converter Register list 888 ADCS0 (ADC0): Address 01A5h (Access: Half-word, Byte) ADCR1 (ADC0): Address 01A6h (Access: Word, Half-word, Byte) ADCR0 (ADC0): Address 01A7h (Access: Word, Half-word, Byte) ADCT1 (ADC0): Address 01A8h (Access: Word, Half-word, Byte) 3.1 A/D Enable Register (ADER) While a pin is used as analog input, corresponding bit in ADER register have to be set to 1. A/D enable register (ADER) ADERH (ADC0): Address 01A0h (Access: Word, Half-word, Byte) ADERL (ADC0): Address 01A2h (Access: Word, Half-word, Byte) 3.2 A/D Control Status Register (ADCS) A/D control status register 1 (ADCS1) A/D control status register 0 (ADCS0) 3.3 Data Register (ADCR1, ADCR0) Data register (ADCR1, ADCR0) 3.4 Sampling Timer Setting Register (ADCT) Sampling timer setting register (ADCT) 3.5 A/D Channel Setting Register (ADSCH, ADECH) A/D channel setting register (ADSCH, ADECH) Page 4. Operation of A/D Converter Single Mode Continuous Mode Stop Mode 4.1 Single-shot conversion mode 4.2 Scan conversion mode 899 5. Setting Table 5-1 Settings needed to use A/D - Single-Shot Conversion Mode Table 5-2 Settings needed to use A/D - Scan Conversion Mode Page Page 6.3 How do I set a conversion time? 6.4 How do I enable analog pin input? 6.5 How do I enable analog pin input for Stepper Motor Controller? 6.6 To select how to activate the A/D converter 6.7 To activate the A/D converter 6.8 To verify the end of a conversion 6.9 How do I read a conversion value? 6.10 How do I force an A/D conversion operation to a stop? 6.11 What interrupt registers are used? 6.12 What interrupts are available? 6.13 How do I enable, disable, clear interrupts? 7. Caution 907 Chapter 44 A/D Converter 7.Caution Definitions of A/D Converter Terms =V(N+1)T - VNT -1 [LSB] 1LSB VNT: Voltage at which digital output transit from (N+1) to N 908 Chapter 45 D/A Converter 910 Chapter 45 D/A Converter AVcc AVss D/A converter (0-1) DA0/P28.6 DA1/P28.7 DADR0/ DADR1 1 0 From Port Data register Port read 4.1 DADR: D/A Data Register 4.2 DACR: D/A Control Register Page Page Page Page 916 8. Caution The table below lists the output voltages of the D/A converter (in 10-bit resolution mode). The table below lists the output voltages of the D/A converte (in 8-bit resolution mode)r. 917 Chapter 46 Alarm Comparator ACSR Figure 2-1 Alarmcomparator (simplied circuit) Chapter 46 Alarm Comparator Alarm comparator - analog part Alarm comparator - digital part 3. Alarm Comparator Control/Status Register (ACSR) 4. Operation Modes 4.1 Interrupt Mode (IEN=1) 4.2 Polling Mode (IEN=0) 4.3 Setting and Resetting of IRQ-Flagbit 4.4 Power Down Modes of the Alarm Comparator Chapter 47 LCD Controller 922 Timing Control Circuit Control Section 0 1 Page 4.1 LCR0: LCDC Control Register 0 925 bit1-0: Frame period Select an appropriate value in accordance with the frame frequency of your LCD panel. 4.2 VRAM: Data Memory for Display Page 4.3 LCR1: LCDC Control Register 1 4.4 LCDCMR: Common Pin Switching Register 5.1 LCD Controller/Driver (LCDC) Operation 5.2 1/2 Duty Cycle Output Waveform Page 5.3 1/3 Duty Cycle Output Waveform Page 933 5.4 1/4 Duty Cycle Output Waveform Page 935 7.1 How do I specify pins as COM or SEG output pins? Page 7.2 How do I set VRM? 7.3 How do I set a frame period? 7.4 How do I set a duty cycle? 7.5 How do I control starting and stopping of LCD? 7.6 How do I enable or disable LCD display? 7.7 How do I enable LCD display even in the sub-stop mode? 7.8 How do I select internal or external divided resistors? 7.9 How do I select internal or external divided resistors? When using internal divided resistors: 7.10 How do I use external divided resistors to shut off the current when LCD is deactivated? Page Chapter 48 Clock Monitor Chapter 48 Clock Monitor Clock Monitor MONCLK Internal clocks Prescaler Selector 943 4.1 Clock Monitor Conguration Register A register for output settings of an internal clock signal CMCFG: Address 04AFH (Access: Byte) bit7-4: Select an output frequency prescaler Page Page 946 *:For each setting procedure, refer to an appropriate section. Use the Output Enable bit (CMCFG.CMSEL[3:0]). 7.1 How do I set an output terminal (MONCLK)? Use the Clock Monitor Selection bits (CMCFG.CMSEL[3:0]) 7.2 How do I select an output frequency? Use the Output Frequency Select bit (CMCFG.CMPRE[3:0]). 7.3 How do I enable/disable clock monitor output? Page Page Chapter 49 Real-Time Clock 950 Chapter 49 Real-Time Clock Oscillation Second Counter Minute Counter Hour Counter WTHR 4.1 WTCR: RTC Control Register Page Page 4.2 WTBR: Sub-Second Registers 4.3 WTHR/WTMR/WTSR: Hour/Minute/Second Registers 956 Chapter 49 Real-Time Clock This section describes Real-time Clock operation. Page Page Page 7.8 What are interrupt-related registers? 7.9 What interrupts are available and how are they selected? 7.10 How do I enable interrupts? Page Page Chapter 50 Subclock Calibration Unit 964 Chapter 50 Subclock Calibration Unit 2.Block Diagram Figure 2-1 Block Diagram of the calibration unit 965 Chapter 50 Subclock Calibration Unit 3.Timing 3. Timing 4. Clocks Clock ratio TOSC32/OSC100 > 2 x TOSC4 + 3 x TCLKP The input frequencies must not exceed the values given in Table 4-1 . Calibration Unit Control Register (CUCR) 32kHz/100kHz Timer Data Register (CUTD) 968 4MHz Timer Data Register (CUTR1/CUTR2) 5.1 Calibration Unit Control Register (CUCR) Page 5.2 32 kHz / 100 kHz Timer Data Register (16 bit) (CUTD) Page 5.3 4 MHz Timer Data Register (24 bits) (CUTR) 32kHz The setting of the 32KHz Timer Data Register can be calculated in the following way. 100kHz The setting of the 100KHz Timer Data Register can be calculated in the following way. Power dissipation: Measurement limits: Chapter 51 Low Voltage Reset/Interrupt 3.1 LV Detection Control Registers 977 LVSEL: Address 04C4h (Access: Byte, Halfword, Word) Bit7-4: External LV detection voltage level Bit3-0: Internal LV detection voltage level Page Chapter 52 Regulator Control 3.1 Regulator Control Registers 981 REGSEL: Address 04CEh (Access: Byte, Halfword, Word) Bit7-6: Reserved bit. The read value is always 0. Bit5: Flash memory supply mode. Note: Please check with the related device datasheet if this setting is supported. Bit4: Main Regulator supply mode. Note: Please check with the related device datasheet if this setting is supported. Bit3-0: Sub-regulator voltage level Page Chapter 53 Fixed Mode-Reset Vector / BOOT-ROM 2. Check for Boot Conditions 2.1 Evaluation Chip MB91V460 Page 2.2 Flash devices of MB91460 series (MB91F46x) 986 Chapter 53 Fixed Mode-Reset Vector / BOOT-ROM 2.Check for Boot Conditions Flow Chart of checking boot conditions on ash derivates of MB91460 series 2.3 Internal Bootloader Description 3. Registers modified by Boot ROM 3.1 Evaluation Chip MB91V460 3.2 Flash devices of MB91460 series 4. Flash Access Mode Switching 5. Bootloader Update Strategy Page Page Chapter 54 Flash Memory This chapter describes the use of the built-in flash memory. 994 Figure 3-1 Block Diagram (32bit ash) 16-bit DQ0 to DQ63 DQ0 to DQ63 DQ0 to DQ31 DQ0 to DQ31 3.1 Address conversion from CPU Mode to Flash Programming Mode 5. Access Modes 5.1 Access from the FR-CPU 64-bit CPU mode (read/execute), not for all devices 32-bit CPU mode (read/write/execute), write not for all devices 16-bit CPU mode (read/write) 6. Flash Access Mode Switching 6.1 Flash Memory Mode 999 7.Auto Algorithms 7. Auto Algorithms Writes and erases to Flash memory are performed by launching the Flash memory's own Auto Algorithms. 7.1 Command Operation Table 7-1 List of Commands in CPU mode 7.2 Auto Algorithm Commands Read/reset command Program (write) Chip erase Sector erase Erase suspend Page 7.3 Hardware Sequence Flag 7.4 FLCR: Hardware Sequence Flag Page 1006 7.Auto Algorithms Figure 7-5 Write/erase Determination Sequence Using Toggle-bit Function 7.5 Sample Use of Hardware Sequence Flag Page Page Chapter 55 Flash Security 3. Flash Security Vectors 3.1 Vector addresses 3.2 Security Vector FSV1 FSV1 (bits 31 to 16) FSV1 (bits 15 to 0) 1012 3.3 Security Vector FSV2 1013 4.1 Flash Security Control Register FSCR0: Address 7100h (Access: Byte (write), Word (read)) FSCR1: Address 7104h (Access: Byte (read), Word (write)) Calculation of the CRC32 start- and end-address: