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TOC

Chapter 1 Introduction......................................................................................... 1

1. How to Handle the Device..................................................................................................... 1
2. Instruction for Users............................................................................................................... 3
3. Caution: debug-related matters............................................................................................. 6
4. How to Use This Document................................................................................................... 7

Chapter 2 MB91460 Rev.A/Rev.B Overview..................................................... 11

1. Overview.............................................................................................................................. 11
2. Features............................................................................................................................... 11
3. MB91460 Series Product Lineup......................................................................................... 19
4. Block Diagram..................................................................................................................... 21

Chapter 3 MB91460 Series Basic Information................................................. 23

1. Memory Map........................................................................................................................ 23
2. I/O Map................................................................................................................................ 24
3. Interrupt Vector Table.......................................................................................................... 73
4. Package............................................................................................................................... 78
5. Pin Assignment Diagram..................................................................................................... 79
6. Pin Definitions...................................................................................................................... 80
7. I/O Circuit Type.................................................................................................................... 94
8. Pin State Table.................................................................................................................... 96

Chapter 4 CPU Architecture............................................................................ 105

1. Overview............................................................................................................................ 105
2. Features............................................................................................................................. 106
3. CPU................................................................................................................................... 107
4. 32-bit/16-bit Bus Converter................................................................................................ 107
5. Harvard/Princeton Bus Converter...................................................................................... 107
6. Instruction Overview.......................................................................................................... 108
7. Data Structure.................................................................................................................... 109
8. Word Alignment................................................................................................................. 110
9. Addressing......................................................................................................................... 111

Chapter 5 CPU Registers................................................................................. 113

1. General-purpose Registers................................................................................................ 113
2. Dedicated Registers.......................................................................................................... 113

Chapter 6 EIT: Exceptions, Interrupts and Traps.......................................... 121

1. Overview............................................................................................................................ 121
2. Features............................................................................................................................. 121
3. EIT Trigger......................................................................................................................... 121
4. Return from EIT................................................................................................................. 121
5. EIT Interrupt Level............................................................................................................. 122