Fujitsu FR60 4.8 FIFO Control Register (FCR04)

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Chapter 32 USART (LIN / FIFO)
4.USART Registers
4.8 FIFO Control Register (FCR04)
Figure 4-8 Configuration of FIFO control registe
76543210 Initial value
0 0 0 0 0 0 0 0B
R/WR/W R/W R/W R/WR R/W R/W
bit 0
SVD select Fifo read valid date status for RX / TX
0 Select reading status from RX FIFO
1 Select reading status from TX FIFO
bit 1
ETX control TX FIFO (on / off)
0 Disables TX FIFO
1 Enables TX FIFO
bit 2
ERX control RX FIFO (on / off)
0 Disables RX FIFO
1 Enables RX FIFO
bit 3
not used / always read 0
bit 4
RXL0 RX Triggerlevel
0RX Triggerlevel Bit 0
bit 5
RXL1 RX Triggerlevel
0RX Triggerlevel Bit 1
bit 6
RXL2 RX Triggerlevel
0RX Triggerlevel Bit 2
bit 7
RXL3 RX Triggerleve
0RX Triggerlevel Bit 3
R/W : Readable and writable
R : Flag is read only, writing to it
has no effect
: Initial value