Hisense LCD42P69P, LCD47P69P MT8222_P1V1 (DDR1)

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet of
MediaTek (ShenZhen) Inc.
Drawn: 1
C
114
MediaTek Confidential
Title
Size Document Number Rev
Date: Sheet of
MediaTek (ShenZhen) Inc.
Drawn: 1
C
114
MediaTek Confidential
Title
Size Document Number Rev
Date: Sheet of
MediaTek (ShenZhen) Inc.
Drawn: 1
C
114
MediaTek Confidential
Low = HP insert
High = WP disable
High = Mute on
ADIN0
ADIN1
ADIN2
ADIN3
ADIN4
ADIN5
GPIO_20
GPIO_21
GPIO_22
GPIO_23
GPIO_24
GPIO_25
HMDI 0 HPLUG DETECT
HMDI 1 HPLUG DETECT
HMDI 2 HPLUG DETECT
High = WP disable
Low = Backlight on
PWM0
PWM1
PWM2
PWM3
UP30
UP31
UP33
UP34
UP35
GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
GPIO_6
GPIO_7
GPIO_8
GPIO_9
GPIO_10
GPIO_11
INT Audio MUX select bit 0
( DDR1 WITH TERMINATION )
Low = Normal power on
LVDS RESERVED
LVDS RESERVED
Hi = LVDS power on
BL ON/OFF CONTROL
MT8222
4052 SWITCH
FCI
FCI
AMP_MUTE CONTROL
LVDS POWER ON/OFF
DIMMING CONTROL
GPIO Definition
GPIO usage
MT8222_P1V1 (DDR1)
NORMAL POWER ON/OFF
Audio MUX
VERSION V1.0
AMP_SD/FCI
SCART1 VIDEO OUTPUT SW/FCI
SFlash
RF Tuner
HDMIx3
Power Distribution
DDR1
VGA
USBx2
Power conversion to 33V
FCI
FCI
FCI
FCI
SYSTEM E2PROM WP
LVDS out
CVBS x 2
S-Video x 1
YPbPr x 2
Analog AMP Speaker
E2PROM
Audio MUX
Jiu.Ni
HDMI/VGA EDID E2PROM WP
Function define
TI3101D (10Wx2)
Headphone
TDA9885
4052 x 2
Micphone
Interface
GAME
GAME
GAME
GAME
SCART FS
SCART FS
4052 SWITCH
KEYPAD
KEYPAD
SPDIFIN
GPIO/BLOCK
HISENSE_MT8222_EU
2008/1/25
MICPHOTO RESERVE
AOSDATA0
AOLRCK
AOBCLK
AOMCLK USB1 PWR ENABLE
USB1 OC TAG
USB0 OC TAG
USB0 PWR ENABLE
4558
Scart x 2
DAC
MCU WT6702
POWER