Beep Code | Description |
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none | CPU register test in progress or failure. |
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CPU Failure | |
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CMOS write/read test in progress or failure. Failure will result in a system | |
| halt. |
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ROM BIOS checksum test in progress or failure. Failure will result in a | |
| system halt. Checksum test - All of the values in a given range of |
| locations are added together. The range includes a location which, when |
| added to sum of the ranges, will produce a known result (0). BIOS is in |
| FLASH and can only be fixed through replacement of the flash device (not |
| a field repairable item) Customer units should be returned for repair. |
|
|
Programmable interval timer 0 test in progress or failure. Failure will | |
| result in a system |
|
|
DMA channel 0 address and count register test in progress or failure. | |
| Failure will result in a system halt. |
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DMA page register write/read test in progress or failure. Failure will result | |
| in a system halt. |
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RAM refresh verification test in progress or failure. Failure will result in a | |
| system halt. |
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SMI RAM Bad. Failure will result in a system halt. | |
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None | First 64K RAM test in progress. No specific test is performed - just |
| indicates that the test is beginning (i.e., no failure). |
|
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First 64K RAM chip or data line failure, | |
| system halt. |
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Parity failure first 64K RAM. Failure results in a system halt. | |
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First 64K RAM chip or data line failure on bit x. Failure results in a system | |
| halt. |
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Slave DMA register test in progress or failure. Failure results in a system | |
| halt. |
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Master DMA register test in progress or failure. Failure results in a system | |
| halt. |
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|
50