2 System Board
PCI Bus Interface | Sequential |
| state burst cycles. The maximum PCI burst transfer can be from 256 bytes to |
| 4 KB. The chip supports advanced snooping for PCI master bursting, and |
| provides a |
| The PCI arbiter supports PCI bus arbitration for up to four masters using a |
| rotating priority mechanism. Its hidden arbitration scheme minimizes |
| arbitration overhead. |
Data Path | Storage elements are provided for bidirectional data buffering among the 64- |
| bit PL data bus, the |
| data bus. |
| There are three FIFO |
| bridges of the PL, PCI, and Memory buses. This buffering is used, partly, to |
| smooth the differences in bandwidths between the three buses, thereby |
| improving the overall system performance. During bus operations between |
| the PL, PCI and Memory buses, the chip receives control signals from the |
| TXC, performs functions such as latching data, forwarding data to |
| destination bus, data assemble and disassemble. |
| Error correcting code (ECC) and parity bits are generated for memory |
| writes, and optional parity checking for memory reads. This operation |
| always sustains zero wait performance on |
| streams zero wait performance on |
| Whilst accesses to the local memory are in progress, whether it be from the |
| PL or PCI bus, the TXC maintains control of the secondary cache, DRAMs, |
| and the datapath. |
This unit controls the L2 cache memory, adopting a write back policy, in a | |
Controller | direct mapped organization. An |
| 64 MB of main memory to be cached (if more than 64 MB of main memory is |
| installed, accesses to the uppermost regions will be made directly to the main |
| memory modules, and not via the cache memory mechanism). When a |
| 512 KB cache memory module is installed, the chip set allows provision for |
| an |
| this facility has not been enabled in the HP BIOS. More details on the use of |
| HP cache memory are given on page 32. |
| The cache memory line width is |
| the |
| line, and so require four |
23