HP Vectra VL 5/xxx 5 manual Cache Memory, Main Memory

2 System Board

Devices on the Processor-Local Bus

Setting the switches to operate at a slower speed, than the processor is capable of supporting, can still cause erratic behavior in some case, and would reduce the instruction throughput in others.

Cache Memory

The computer supports two levels of cache memory, each with a 32-byte line width. The Level-1 (L1) cache memory is fabricated on the processor chip. The Level-2 (L2) cache memory is a slower module on the system board.

Each acts as temporary storage for data and instructions from the main memory. Since the system is likely to use the same, or adjacent, data several times, it is faster to get it from the on-chip or on-board cache memory than from the main memory.

The L1 cache memory is divided into two separate banks: an L1 I-cache for instruction words, and an L1 D-cache for data words. On a P54 processor, each has a capacity of 8 KB; on an MMX (P55) processor, each has a capacity of 16 KB.

The L2 cache memory is controlled by the PL/PCI bridge chip in the system board chip-set (see page 23 for a description, and details of timing patterns and tag size). A single HP cache memory module consists of 256 KB or

512 KB of direct mapped, write-back, synchronous pipelined burst, 8.5 ns static random access memory (SRAM). The chip-set does not support asynchronous or burst SRAM modules.

Main Memory

There are six main memory module sockets, arranged in three banks (A to C). One bank is already occupied by the pair of single interline memory modules (SIMMs) that contain the 16 MB or 32 MB of memory that is supplied with the computer.

Different banks can have different capacities (8, 16, 32 or 64 MB), but must be composed of identical pairs of modules (2✕4, 2✕8, 2✕16 or 2✕32 MB). By installing a pair of 32 MB SIMMs in every bank, first removing the memory modules that were supplied with the computer, the maximum capacity of 192 MB of main memory can be attained.

The banks can be filled, or left empty, in any order. However, there is a performance advantage to filling the banks in the order A, B, C. The explanation for this is outlined in the description of the cache memory controller on page 23.

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