4 Summary of the HP/Phoenix BIOS
BIOS Addresses
The PCI interrupt lines A, B, C and D are spread across the four inputs of the interrupt router (which is part of the PCI/ISA bridge, in the PIIX3 chip). Since most PCI devices are
Integrated |
| Slot 1 |
| Slot 2 |
| Slot 3 or R |
| Slot 4 (MT) |
graphics |
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A |
| A B C D |
| A B C D |
| A B C D |
| A B C D |
A
B PCI/ISA
Bridge
C
D
PCI interrupts are then mapped into ISA interrupts inside the PCI/ISA
Bridge (in the PIIX3 chip), by configuring registers 60h through 63h.
Bit | Description |
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7 | Routing of interrupts: when enabled, this bit routes the PCI interrupt signal to the PC- |
| compatible interrupt signal specified in bits[3:0]. At reset, this bit is disabled (set to 1) |
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6:4 | Reserved: read as 000 |
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3:0 | IRQx# Routing Bits: these bits specify which IRQ signal to generate. |
| Possible values are: 3, 4, 5, 6, 7, 9, 10, 11, 12, 14, 15. |
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The possible choices given by the Setup program are 9, 10, 11, 15. If some of these are unavailable due to ISA cards, some interrupts will have to be shared.
The IDE controller is actually configured in legacy mode, and uses IRQ 14 (IRQ 15 for the secondary channel). The mode setting is in configuration byte 09h of the IDE controller, device 01h.
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