IBM 6268, 6288, 6278 manual IDE bus master interface, USB interface, Bus

Chapter 2. System board features

ŸDelayed transaction

ŸPCI parity checking and generation support

IDE bus master interface

The system board incorporates a PCI-to-IDE interface thatAT Attachmentcomplies Inwitherfacethe with Extensions.

The bus

masterfor the IDE interface

is integrated into the I/O hub of the Intel

PCI

2.1

compliant.

It

connects

directly

to

the

PCI

bus

and

is

designed

to allow

co

the

PCI

bus and IDE bus. The chip

set is capable of supporting PIO mode 0–4 devi

mode

0–3

devices, ATA 66 transfers up to 66 Mbytes/sec.

The

IDE

devices

receive

their

power

through a four-position

power

cable

containing

+

voltage.

When

adding

devices

to

the

IDE

interface,

one

device

is

designated

as

th

another

is designated

as

the slave

or

subordinate device. These designations are

d

or jumpers on each device. There are

two

IDE

ports,

one designated 'Primary'

and

th

allowing for

up

to

four

devices

to

be

attached. The

total

number

of

physical

IDE

d

the

mechanical

package

to

a

maximum

of

four.

For

the

IDE

interface,

no

resource

assignments

are

given

in

the

system

memory

or

the

access

(DMA)

channels. For

information

on

the resource assignments, see “Input/output

add

page 36

and

Figure 36

on

page 40

(for

IRQ

assignments).

USB interface

Universal

serial bus (USB) technology is a standard feature of the computer. The s

the USB

interface

with

two

connectors

integrated

into

the

ICH (I/O controller

hub)

USB-enabled device can attach to

each

connector,

and

if

that device is a hub, mul

attach to the hub and be used

by

the

system. The

USB

connectors

use Plug and

Play

installed

devices. The

speed

of

the

USB

is

up

to 12 Mbps with a

maximum of

127

p

is compliant with Universal Host Controller Interface Guide 1.0.

Features

provided

by

USB

technology

include:

Ÿ

Support

for hot-pluggable devices

Ÿ

Support

for

concurrent

operation

of

multiple

devices

Ÿ

Suitable for

different

device

bandwidths

Ÿ

Support

for

up

to

five

meters

length

from

host

to

hub

or from hub to hub

Ÿ

Guaranteed bandwidth

and

low latencies

appropriate

for

specific

devices

Ÿ

Wide

range

of

packet

sizes

ŸLimited power to hubs

For information on the connector pin assignments for the USB interface, see “USB port page 33.

Low

pin

count

(LPC)

bus

On

the

system

board, the Intel ICH1 bridge provides the interface between the p

interface

(PCI) and

LPC buses. The chip set is

used to convert PCI bus

cycles

to

chip set

also

includes all

the subsystems

of the ISA bus,

including two

cascaded in

DMA

controllers

with

four 8-bit and three 16-bit

channels,

three counters

equivalent

to

interval

timer,

and

power

management. The PCI

bus

operates

at

33 MHz.

Chapter 2. System board features5