IBM 6288, 6268, 6278 manual System memory, PCI bus, Sdram, Dimm

Chapter 2. System board features

System memory

The

system memory

interface

is

controlled

by

the

Intel

82810

chip

set. PCI

100

synchro

random

access

memory

(SDRAM)

is

standard.

The

maximum

amount

of

system

memory is 512 MB. For

memory

expansion,

the

system

board

pr

two

dual

inline

memory

module

(DIMM)

connectors.

100

MHz DIMMs

in

sizes of 32

MB,

64

MB,

and

256

MB

are

supported. The

amount

of

memory

preinstalled

varies

by

model.

The following information applies to system memory:

Ÿ

SDRAM,

nonparity, unbuffered,

3.3V memory

is

standard.

Ÿ

The

maximum

height

of

memory

modules

is

6.35

cm

(2.5

in.).

Ÿ

Only

PC

100

industry-standard,

gold-contact DIMMs are supported.

Ÿ

The

PC

300GL

does

not

support

error

correcting

code

(ECC).

ŸAuto-configure, auto-detect maximum system memory, using serial presence detect and co interface (BIOS specific).

For information on the pin assignments for the memory module connectors, see “Memory connec page 25.

The following figure shows some possible configurations for the supported DIMMs.

Note: Values in the following table are represented in megabytes (MB).

Figure 1.	Memory configurations
Total	memory (MB)	DIMM 0		DIMM 1
	32		32	0
	64		32	32
	64		64	0
	96		64	32
	128		64	64
	128		128	0
	160		128	32
	192		128	64
	256		128	128
	384		256	128
	512		256	256

PCI bus

The fully synchronous 33 MHz PCI bus originates in the Intel 82801 chip. Features of t

Ÿ	Integrated arbiter		with multitransaction PCI arbitration acceleration		hooks
Ÿ	Zero-wait-state, microprocessor-to-PCI write interface for high			performance graphics
Ÿ	Built-in PCI bus arbiter with support for up to five masters
Ÿ	Microprocessor-to-PCI memory write posting with 5-Dword-deep buffers
Ÿ	Converts back-to-back		sequential microprocessor-to-PCI memory write	to PCI burst		write
Ÿ	PCI-to-DRAM posting 18		Dwords
Ÿ	PCI-to-DRAM up to 100+ MB/sec bandwidth
Ÿ	Multitransaction	timer	to support multiple short PCI transactions	within	one PCI	ARB cycl
Ÿ	PCI 2.2/2.3	compliant

4 Technical Information Manual