IBM 6288, 6268, 6278 manual System compatibility, Hardware compatibility, Hardware interrupts, Eoi

Chapter 6. System compatibility

Chapter 6. System compatibility

This chapter discusses some of the hardware, software, and BIOS compatibility issues

Refer CompatibilitytoReportfor a list of compatible hardware and software options.

Hardware compatibility

This section discusses hardware, software, and BIOS compatibility issues that must be designing application programs.

Many	of the	interfaces	are the	same	as those used by	the IBM Personal Computer AT.
the	command	and status	organization	of	these interfaces is	maintained.

The functional interfaces are compatible with the following interfaces:

Ÿ	Intel	8259 interrupt controllers (edge-triggered mode)
Ÿ	National	Semiconductor	NS16450 and NS16550A serial communication controllers
Ÿ	Motorola	MC146818 Time	of	Day	Clock	command	and status (CMOS	reorganized)
Ÿ	Intel	8254 timer, driven		from	a	1.193	MHz clock (channels	0, 1, and 2)

ŸIntel 8237 DMA controller, except for the Command and Request registers and the Rota

functions; the Mode register is partially supported

Ÿ	Intel	8272 or 82077 diskette		drive	controllers
Ÿ	Intel	8042 keyboard	controller	at	addresses	hex	0060 and	hex	0064
Ÿ	All video standards using VGA,			EGA,	CGA, MDA, and Hercules modes
Ÿ	Parallel	printer ports	(Parallel	1,	Parallel 2,	and	Parallel	3) in	compatibility mode

Use the above information to develop application programs. Whenever possible, use the B interface to hardware to provide maximum compatibility and portability of applications a

Hardware interrupts

Hardware interrupts are level-sensitive for PCI interrupts. The interrupt controller clears register bit when the interrupt routine sends an End-of-Interrupt (EOI) command to the command is sent regardless of whether the incoming interrupt request to the controller inactive.

The interrupt-in-progress latch is readable at an I/O-address bit position. This latch i interrupt service routine and might be reset by the read operation or it might requ

Note: For performance and latency considerations, designers might want to limit the number sharing an interrupt level.

With level-sensitive interrupts, the interrupt

controller requires that the

interrupt

requ

time the

EOI

command

is

sent;

otherwise,

a

new interrupt

request

will be detected. To

level-sensitive

interrupt

handler

must

clear

the interrupt condition (usually by a read

an I/O

port

on the

device causing

the

interrupt). After

processing

the

interrupt,

the

1.Clears the interrupt

2.Waits one I/O delay

22  Copyright IBM Corp. September 1999