Buffer Q3

4-3 PLL CIRCUITS

4-3-1 GENERAL

PLL circuits control TX and RX VCO circuits. IC1 is a PLL IC and contains prescaler, programmable counter, programmable divider, phase detector, charge pump in its package.

The VCOs directly generate the transmit frequency and the 1st LO frequency for receiving. The PLL sets the divided ratio based on the serial data from the CPU (IC661), and compares the phase of the VCO output with the reference oscillator's frequency (15.3 MHz) oscillated by X1.

If the oscillated signal drifts, the phase of its frequency changes from the phase of the reference frequency, causing a lock voltage change to compensate for the drift in the oscillated frequency.

4-3-2 TRANSMIT LOOP

A portion of the generated signal at the TX VCO (Q51, D35– D39) is applied to the PLL IC (IC1, pin 8) via buffer-amplifier (Q71). The applied signal is divided at the prescaler section and programmable divider section and is then applied to the phase detector section.

The phase detector compares the input signal with the reference frequency, and then outputs the control signal (pulse-type) from pin 5 via the charge pump section. The pulse-type signal is converted into DC voltage at the loop filter (R17–R19, C16, C17), and then applied to the TX VCO (Q51, D35–D39) as the lock voltage.

4-3-3 RECEIVE LOOP

The generated signal at the RX VCO (Q41, D31–D34) is applied to the PLL IC (IC1, pin 8) via buffer-amplifier (Q71) and is divided at the prescaler section and programmable divider section and is then applied to the phase detector section.

The phase detector compares the input signal with a reference frequency, and then outputs the control signal (pulse-type) from pin 5. The pulse-type signal is converted into DC voltage at the loop filter (R17–R19, C16, C17), and then applied to the RX VCO (Q41, D31–D34) as the lock voltage.

•PLL CIRCUITS

"LOINV" signal

to the CPU (IC661, pin 34)

RX VCO

 

 

Buffer

D92

 

 

to 1st mixer circuit

 

 

Q62

 

 

 

Q41, D31–D34

Buffer

 

D91

 

 

to transmitter circuit

 

Q61

 

TX VCO

 

 

 

 

 

 

 

Buffer

 

 

 

Q71

 

Q51, D35–D39

 

 

 

Loop

LPF

filter

 

 

IC1 MB15A02PFV

30.6MHz 2nd LO signal to the FM IF IC (IC231, pin 2)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8

 

 

 

 

 

5

 

Charge

 

 

Programmable

 

Prescaler

 

 

 

 

 

 

 

 

 

 

 

pump

 

 

 

divider

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

9

 

SCLK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Phase

 

 

 

Shift register

 

 

10

 

SDATAO

PLL control signals

 

 

 

 

detector

 

 

 

 

 

 

 

from D/A converter (IC251, pins 6–7)

 

 

 

 

 

 

 

 

 

11

 

 

 

 

 

 

 

 

 

 

PLSTBO

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

 

 

15.3 MHz reference signal

 

 

 

 

 

 

 

 

 

 

 

 

 

 

×2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

from reference frequency osciilator (X1)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Q221

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