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ICP DAS USA SAGP-845EV manual Advanced Chipset Features, By SPD

Models: SAGP-845EV

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4.7 Advanced Chipset Features

4.7 Advanced Chipset Features

CMOS Setup Utility – Copyright © 1984 – 2000 Award Software

Advanced Chipset Features

DRAM Timing Selectable			By SPD			Item Help
CAS Latency Time			1.5			_______________________
Active to Precharge Delay		7				Menu Level ¾
DRAM RAS# to CAS# Delay		3
DRAM RAS# Precharge		3
Memory Frequency For		AUTO
System BIOS Cacheable		Enabled
Video BIOS Cacheable		Disabled
Memory Hole At 15M-16M		Disabled
Delayed Transaction		Enabled
AGP Aperture Size		64MB

	Onboard Display Cache Setting
	On-chip VGA	Enabled
Flash BIOS		Disabled
↑↓←→Move Enter: Select		+/-/PU/PD:				Value F10:Save ESC: Exit
F1:General Help
F5:Previous Values F6:Fail-safe defaults						F7:Optimized Defaults

This section allows users to configure the system based on the specific features of the installed chipset. This chipset manages bus speeds and accesses to system memory resources, such as DRAM and the external cache. It also coordinates communications between the conventional ISA bus and the PCI bus. It must be stated that these items should never need to be altered. The default settings have been chosen because they provide the best operating conditions for the system.

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ICP DAS USA SAGP-845EV manual Advanced Chipset Features, By SPD

Contents

PCB Version Manual Version SAGP-845EV SOCKET 478 PENTIUM 4 with10/100 Ethernet LAN & AGP4X VGA SBC cCopyright 2003 by ICP Electronics Inc. All rights ReservedSupport Copyright NoticeTrademarks SUPPORT@IEI.COM.TWAWARD BIOS SETUP Table of ContentsINSTALLATION INTRODUCTIONAPPENDIX A WATCHDOG TIMERAPPENDIX C. HOW TO UPGRADE A NEW BIOS APPENDIX B1. Introduction 1.1 Specifications IrDA port Watchdog timermouse connector USB portRecommended 350-watt or higher output power Power consumption2. Please use ATX-12V power connector PW2 to provide power to the CPU Operating1.2 Package Contents 2. Installation 2.1 SAGP-845EV s LayoutLayout 2.4 Compact Flash Card Master/Slave Mode Setting 2.2 Clear CMOS Setup2.3 Keyboard Power Selection JP2 Clear CMOS SetupLABEL 3. ConnectionTable of Connectors FUNCTIONPIN NO 3.1 Floppy Disk Drive ConnectorFDD1 FDC CONNECTOR DESCRIPTIONPIN NO 3.2 Ultra ATA33/66/100 IDE Disk Drive ConnectorIDE1 Primary IDE Connector DESCRIPTIONDESCRIPTION IDE2 Secondary IDE ConnectorPIN NO PIN NOPIN NO 3.3 Parallel PortLPT1 Parallel Port Connector DESCRIPTION3.4 Serial Ports COM1 10-pin Connector PIN NO. DESCRIPTIONCOM2 10-pin Connector PIN NO. DESCRIPTION 3.5 Keyboard Connector3.6 USB Port Connector KBM1 6-pin Mini-DIN Keyboard/Mouse ConnectorUSB3 dual port 3.7 IrDA Infrared Interface PortIR1 IrDA connector PIN NO. DESCRIPTION PIN NoFAN1/FAN2/FAN3 CPU Fan Connector 3.8 Fan Connector3.9 LAN RJ45 Connector LAN1 LAN RJ45 ConnectorVGA1 15-pin Female Connector PIN NO. DESCRIPTION PIN NO. DESCRIPTION 3.10 VGA Connector3.11 Audio Connectors CN4 Audio Connector 2x82.00mmPIN NO 3.12 Compact Flash Storage Card SocketCFA1 Compact Flash Storage Card Socket pin assignment DESCRIPTIONPW2 ATX12V Power Connector for CPU 3.13 External Switches and IndicatorsPW1 ATX Power Switch Connector PIN NO. DESCRIPTION CN2 Multiple Panel4.1 Introduction 4. Award BIOS Setup4.2 Starting Setup Press DEL to enter SETUP4.3 Using Setup 4.4 Main Menu Advanced BIOS Features 4.4.1 Setup ItemsStandard CMOS Features Advanced Chipset FeaturesSave & Exit Setup Load Optimized DefaultsSupervisor / User Password Exit Without Save4.5 Standard CMOS Setup Description Main Menu SelectionsOptions IDE Adapters Table 3 Hard disk OptionsDescription selections4.6 Advanced BIOS Features First/Second/Third/Other Boot Device Quick Power On Self TestLAN BootROM Virus WarningTypematic Rate Setting Boot Up Floppy SeekBoot Up NumLock Status Swap Floppy DriveReport No FDD For Win Security OptionOS Select For DRAM 64MB Small LogoEPA Show4.7 Advanced Chipset Features By SPDDRAM Cycle Time Tras/Trc DRAM Timing SelectableCAS Latency Time DRAM RAS# to CAS# DelayFlash BIOS System BIOS CacheableVideo BIOS Cacheable Memory Hole At 15M-16M4.8 Integrated Peripherals Note There are some item in bottom of scrollIDE Primary/Secondary Master/Slave UDMA On-Chip Primary/Secondary PCI IDEIDE Primary/Secondary Master/Slave PIO USB ControllerOnboard FDC Controller Watchdog Timer UnitIDE HDD Block Mode Onboard Serial Port 1/Port4.9 Power Management Setup Video Off Method Power ManagementAVAILABLE FOR SL CPU’s Video Off In SuspendSuspend Mode HDD Power DownSuspendType PM EVENTS4.10 PnP/PCI Configuration Setup Reset Configuration DataIRQ3/4/5/7/9/10/11/12/14/15 assigned to Resource controlled byIRQ Resources PCI/VGA Palette Snoop4.11 PC Health Status ↑↓←→ MoveSpread Spectrum 4.12 Frequency/Voltage ControlAuto Detect PCI Clk CPU Host / 3V66 / PCI ClockLoad Optimized Defaults 4.13 Defaults MenuLoad Fail-Safe Defaults 4.14 Supervisor/User Password Setting Save to CMOS and EXIT Y/N? Y 4.15 Exit SelectingSave & Exit Setup Exit Without SavingAppendix A. Watchdog Timer INT 15H AH - 6FHExample program INITIAL TIMER PERIOD COUNTERdisable Watchdog Timer ADD YOUR APPLICATION PROGRAM HEREI/O address Range Appendix B. Address MappingIO Address Map DescriptionDMA Channel Assignments 1st MB Memory Address MapIRQ Mapping Table Memory addressAppendix C. How to Upgrade a New BIOS 8. Enter a name for the OLD BIOS file and hit enter OLDBIOS.BIN7. To save the old BIOS, hit Y for yes Recovering the previous BIOS Install screen Appendix D. AGP slot