10 Specification Update
BU34 XXNo FixProcessor May Fail to Acknowledge a TLP Request
BU35 XXNo FixAn Unexpected PMI May Occur After Writing a Large Value to IA32_FIXED_CTR2
BU36 XXNo Fix
A Write to the IA32_FIXED_CTR1 MSR May Result in Incorrect Value in Certain
Conditions
BU37 XXNo FixPCIe* LTR Incorrectly Reported as Being Supported
BU38 XXNo FixPerfMon Overflow Status Can Not be Cleared After Certain Conditions Have Occurred
BU39 XXNo Fix
#GP May be Signaled When Invalid VEX Prefix Precedes Conditional Branch
Instructions
BU40 XXNo FixInterrupt From Local APIC Timer May Not Be Detectable While Being Delivered
BU41 XXNo FixPCI Express* Differential Peak-Peak Tx Voltage Swing May Violate the Specification
BU42 XXNo Fix
PCMPESTRI, PCMPESTRM, VPCMPESTRI and VPCMPESTRM Always Operate with
32-bit Length Registers
BU43 XXNo FixMultiple Performance Monitor Interrupts are Possible on Overflow of Fixed Counter 0
BU44 XXNo FixIA32_FEATURE_CONTROL MSR May be Uninitialized on a Cold Reset
BU45 XXNo Fix
DR6.B0-B3 May Not Report All Breakpoints Matched When a MOV/POP SS is
Followed by a REP MOVSB or STOSB
BU46 XXNo Fix
Setting Hardware Autonomous Speed Disable Configuration Bit Will Block Initial Speed
Upgrade
BU47 XXNo FixLTR Message is Not Treated as an Unsupported Request
BU48 XXNo Fix
64-bit REP MOVSB/STOSB May Clear The Upper 32-bits of RCX, RDI And RSI Before
Any Data is Transferred
BU49 XXNo Fix
An Interrupt Recognized Prior to First Iteration of REP MOVSB/STOSB May Result
EFLAGS.RF Being Incorrectly Set
BU50 XXNo Fix
Accessing Physical Memory Space 0-640K through the Graphics Aperture May Cause
Unpredictable System Behavior
BU51 XXNo FixPEBS May Unexpectedly Signal a PMI After The PEBS Buffer is Full
BU52 XXNo FixInstructions Retired Event May Over Count Execution of IRET Instructions
BU53 XXNo FixPCIe* Link May Unexpectedly Exit Loopback State
BU54 XXNo FixThe RDRAND Instruction Will Not Execute as Expected
BU55 XXNo Fix
A PCIe* Device That Initially Transmits Minimal Posted Data Credits May Cause a
System Hang
BU56 XXNo FixPCI Express* Gen3 Receiver Return Loss May Exceed Specifications
BU57 XXNo FixDirect Access Via VT-d to The Processor Graphics Device May Lead to a System Hang
BU58 XXNo Fix
An Event May Intervene Before a System Management Interrupt That Results from IN
or INS
BU59 XXNo Fix
PCIe* May Associate Lanes That Are Not Part of Initial Link Training to L0 During
Upconfiguration
BU60 XXNo Fix
The Processor May Not Comply With PCIe* Equalization Preset Reflection
Requirements for 8 GT/s Mode of Operation
BU61 XXNo FixProcessor May Issue PCIe* EIEOS at Incorrect Rate
BU62 XXNo Fix
Reduced Swing Output Mode Needs Zero De-emphasis to be Supported in PCIe* 5GT/
s Speed
Errata (Sheet 3 of 5)
Number Steppings Status ERRATA
E-1 L-1