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Intel BX80638I53320M BU103. Spurious VT-d Interrupts May Occur When the PFO Bit is Set

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Specification Update 49

corresponding counter with the same number on the physical core’s other thread rather

than the thread experiencing the event. Processors with SMT disabled in BIOS are not

affected by this erratum.

The list of affected memory at-retirement events is as follows:

MEM_UOP_RETIRED.LOADS

MEM_UOP_RETIRED.STORES

MEM_UOP_RETIRED.LOCK

MEM_UOP_RETIRED.SPLIT

MEM_UOP_RETIRED.STLB_MISS

MEM_LOAD_UOPS_RETIRED.HIT_LFB

MEM_LOAD_UOPS_RETIRED.L1_HIT

MEM_LOAD_UOPS_RETIRED.L2_HIT

MEM_LOAD_UOPS_RETIRED.LLC_HIT

MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS

MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT

MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM

MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS

MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE

MEM_LOAD_UOPS_RETIRED.LLC_MISS

MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM

MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM

MEM_LOAD_UOPS_RETIRED.L2_MISS

Implication: Due to this erratum, certain performance monitoring event may produce unreliable

results when SMT is enabled.

Workaround: None identified.

Status: For the steppings affected, see the Summary Tables of Changes.

BU102. The Corrected Error Count Overflow Bit in IA32_ MC0_STATUS is Not Updated After a UC Error is Logged

Problem: When a UC (uncorrected) error is logged in the IA32_MC0_STATUS MSR (401H),

corrected errors will continue to update the lower 14 bits (bits 51:38) of the Corrected

Error Count. Due to this erratum, the sticky count overflow bit (bit 52) of the Corrected

Error Count will not get updated after a UC error is logged.

Implication: The Corrected Error Count Overflow indication will be lost if the overflow occurs after an

uncorrectable error has been logged.

Workaround: None identified.

Status: For the steppings affected, see the Summary Tables of Changes.

BU103. Spurious VT-d Interrupts May Occur When the PFO Bit is Set

Problem: When the PFO (Primary Fault Overflow) field (bit [0] in the VT-d FSTS [Fault Status]

register) is set to 1, further faults should not generate an interrupt. Due to this

erratum, further interrupts may still occur.

Implication: Unexpected Invalidation Queue Error interrupts may occur. Intel has not observed this

erratum with any commercially available software.

Workaround: Software should be written to handle spurious VT-d fault interrupts.

Status: For the steppings affected, see the Summary Tables of Changes.

Contents

Main Page Contents Page Revision History Preface Affected Documents Related Documents Nomenclature Summary Tables of Changes Codes Used in Summary Tables Stepping Page Status Errata (Sheet 2 of 5) Errata (Sheet 3 of 5) Errata (Sheet 4 of 5) Specification Changes Specification Clarifications Documentation Changes Errata (Sheet 5 of 5) Page Identification Information Component Identification using Programming Interface The processor stepping can be identified by the following register contents: Component Marking Information Table 1. Processor Identification (Sheet 2 of 6) Table 1. Processor Identification (Sheet 3 of 6) Table 1. Processor Identification (Sheet 4 of 6) Table 1. Processor Identification (Sheet 5 of 6) Table 1. Processor Identification (Sheet 6 of 6) Errata BU1. The Processor May Report a #TS Instead of a #GP Fault BU3. IO_SMI Indication in SMRAM State Save Area May be Set Incorrectly BU4. Performance Monitor SSE Retired Instructions May Return Incorrect Values BU5. IRET under Certain Conditions May Cause an Unexpected Alignment Check Exception BU6. Performance Monitoring Event FP_MMX_TRANS_TO_MMX May Not Count Some Transitions BU7. General Protection Fault (#GP) for Instructions Greater than 15 Bytes May be Preempted BU8. LBR, BTS, BTM May Report a Wrong Address when an Exception/ Interrupt Occurs in 64-bit Mode BU10. Values for LBR/BTS/BTM Will be Incorrect after an Exit from SMM BU11. EFLAGS Discrepancy on Page Faults and on EPT-Induced VM Exits after a Translation Change BU12. B0-B3 Bits in DR6 For Non-Enabled Breakpoints May be Incorrectly Set BU13. MCi_Status Overflow Bit May Be Incorrectly Set on a Single Instance of a DTLB Error BU14. Debug Exception Flags DR6.B0-B3 Flags May be Incorrect for Disabled Breakpoints BU15. LER MSRs May Be Unreliable BU16. Storage of PEBS Record Delayed Following Execution of MOV SS or STI BU17. PEBS Record not Updated when in Probe Mode BU18. MONITOR or CLFLUSH on the Local XAPIC's Address Space Results in Hang BU19. Faulting MMX Instruction May Incorrectly Update x87 FPU Tag Word BU20. An Uncorrectable Error Logged in IA32_CR_MC2_STATUS May also Result in a System Hang BU23. APIC Error Received Illegal Vector May be Lost BU25. Reported Memory Type May Not Be Used to Access the VMCS and Referenced Data Structures BU27. Fault Not Reported When Setting Reserved Bits of Intel VT-d Queued Invalidation Descriptors BU29. VMREAD/VMWRITE Instruction May Not Fail When Accessing an Unsupported Field in VMCS BU30. Spurious Interrupts May be Generated From the Intel VT-d Remap Engine BU33. Clock Modulation Duty Cycle Cannot be Programmed to 6.25% BU34. Processor May Fail to Acknowledge a TLP Request BU35. An Unexpected PMI May Occur After Writing a Large Value to IA32_FIXED_CTR2 BU36. A Write to the IA32_FIXED_CTR1 MSR May Result in Incorrect Value in Certain Conditions BU37. PCIe* LTR Incorrectly Reported as Being Supported BU38. PerfMon Overflow Status Can Not be Cleared After Certain Conditions Have Occurred BU39. #GP May be Signaled When Invalid VEX Prefix Precedes Conditional Branch Instructions BU40. Interrupt From Local APIC Timer May Not Be Detectable While Being Delivered BU41. PCI Express* Differential Peak-Peak Tx Voltage Swing May Violate the Specification BU42. PCMPESTRI, PCMPESTRM, VPCMPESTRI and VPCMPESTRM Always Operate with 32-bit Length Registers BU43. Multiple Performance Monitor Interrupts are Possible on Overflow of Fixed Counter 0 BU44. IA32_FEATURE_CONTROL MSR May be Uninitialized on a Cold Reset BU46. Setting Hardware Autonomous Speed Disable Configuration Bit Will Block Initial Speed Upgrade BU47. LTR Message is Not Treated as an Unsupported Request BU51. PEBS May Unexpectedly Signal a PMI After The PEBS Buffer is Full BU52. Instructions Retired Event May Over Count Execution of IRET Instructions BU53. PCIe* Link May Unexpectedly Exit Loopback State BU54. The RDRAND Instruction Will Not Execute as Expected BU55. A PCIe* Device That Initially Transmits Minimal Posted Data Credits May Cause a System Hang BU56. PCI Express* Gen3 Receiver Return Loss May Exceed Specifications BU57. Direct Access Via VT-d to The Processor Graphics Device Ma y Lea d to a System Hang BU58. An Event May Intervene Before a System Management Interrupt That Results from IN or INS BU61. Processor May Issue PCIe* EIEOS at Incorrect Rate BU62. Reduced Swing Output Mode Needs Zero De-emphasis to be Supported in PCIe* 5GT/s Speed BU63. PCIe* Root-port Initiated Compliance State Transmitter Equalization Settings May be Incorrect BU64. PCIe* Controller May Incorrectly Log Errors on Transition to RxL0s BU66. PCIe* Link Width May Degrade After a Warm Reset BU67. MSR_PKG_Cx_RESIDENCY MSRs May Not be Accurate BU68. Execution of Package C7 May Result in a Hang BU69. PCIe* Link May Not Enter Loopback.Active When Directed BU71. Unexpected #UD on VZEROALL/VZEROUPPER BU72. PCIe* Root Port May Not Initiate Link Speed Change BU73. Successive Fixed Counter Overflows May be Discarded BU74. Execution of FXSAVE or FXRSTOR With the VEX Prefix May Produce a #NM Exception BU75. VM Exits Due to NMI-Window Exiting May Not Occur Following a VM Entry to the Shutdown State BU77. PCIe* Controller May Not Properly Indicate Link Electrical Idle Condition BU78. PCIe* Controller May Not Enter Loopback BU79. Link Margin Characterization May Hang Link BU80. Unused PCIe* Lanes May Report Correctable Errors BU81. RDMSR of IA32_PERFEVTSEL{4-7} May Return Erroneous Information BU82. PCIe* Link May Fail Link Width Upconfiguration BU83. Graphics L3 Cache Parity Errors May Not be Detected BU85. Graphics L3 Cache Redundancy May Not Behave as Expected BU86. REP MOVSB May Incorrectly Update ECX, ESI, and EDI BU87. Performance-Counter Overflow Indication May Cause Undesired Behavior BU88. RDMSR of IA32_PERFEVTSEL4-7 May Return an Incorrect Result BU89. VEX.L is Not Ignored with VCVT*2SI Instructions BU91. Concurrently Changing the Memory Type and Page Size May Lead to a System Hang BU92. MCI_ADDR May be Incorrect For Cache Parity Errors Page BU99. IA32_MC5_CTL2 is Not Cleared by a Warm Reset BU101. Performance Monitor Counters May Produce Incorrect Results BU103. Spurious VT-d Interrupts May Occur When the PFO Bit is Set Page Page Page Specification Changes Specification Clarifications Documentation Changes BU1.