38 Specification Update
BU59. PCIe* May Associate Lanes That Are Not Part of Initial Link Training to L0 During Upconfiguration
Problem: The processor should not associate any lanes that were not part of the initial link
training in subsequent upconfiguration requests from an endpoint. Due to this erratum,
the processor may associate any Lane that has exited Electrical Idle, even if it is
beyond the width of the initial Link training.
Implication: Upconfiguration requests may result in a Link wider than the initially-trained Link.
Workaround: Endpoints must ensure that upconfiguration requests do not request a Link width wider
than that negotiated during initial Link training.
Status: For the steppings affected, see the Summary Tables of Changes.
BU60. The Processor May Not Comply With PCIe* Equalization Preset Reflection Requirements for 8 GT/s Mode of Operation
Problem: In endpoint-initiated transitions to Polling.Compliance at the 8 GT/s transfer rate, the
processor must reflect, in its ordered sets, the Transmitter Preset requested by the
endpoint regardless of preset legality. Due to this erratum, the processor will reflect the
Transmitter Preset in use after an endpoint requests a reserved Transmitter Preset
rather than the requested preset.
Implication: Endpoints requiring reserved Transmitter Presets to be reflected may be adversely
affected. Intel has not observed failures due to this erratum with any commercially
available devices.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
BU61. Processor May Issue PCIe* EIEOS at Incorrect Rate
Problem: When initiating a Secondary Bus Reset or Link Disable procedure while a PCIe Link is in
Recovery state, the processor should send an EIEOS (Electrical Idle Exit Ordered Set)
after every 32 TS (Training Set) Ordered Sets. Due to this erratum, the processor may
send an EIEOS after every 33 TS Ordered Sets.
Implication: The processor may send an incorrect number of TS Ordered Sets between two EIEOS
Ordered Sets when it initiates Secondary Bus Reset or Link Disable. Intel has not
observed any failures with commercially available devices due to this erratum.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
BU62. Reduced Swing Output Mode Needs Zero De-emphasis to be Supported in PCIe* 5GT/s Speed
Problem: It may not be possible to support the PCIe Transmitter Preset 1 and/or Transmitter
Preset 0 equalization requests in Phase 0 or Phase 2 of Recovery.Equalization LTSSM
states when operating in 8GT/s in reduced or half swing mode, if 0dB transmitter de-
emphasis needs to be supported when operating at 5GT/s.
Implication: This erratum does not affect normal full swing mode of operation. Endpoints requiring
0dB support in half-swing mode should avoid requesting Transmitter Preset 1 and/or
Transmitter Preset 0 as preset requests in Phase 0 or Phase 2 of Recovery.Equalization
when operating in 8GT/s.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.