Intel IP-4MTS6B manual Dram Timing Selectable, CAS Latency Time

Award BIOS Setup

3.6 Advanced Chipset Features

This section allows you to configure the system based on the specific features of the installed chipset. This chipset manages bus speeds and access to system memory resources, such as DRAM and the external cache. It also coordinates communications between the conventional ISA bus and the PCI bus. It must be stated that these items should never need to be altered. The default settings have been chosen because they provide the best operating conditions for your system. The only time you might consider making any changes would be if you discovered that data was being lost while using your system.

Phoenix - AwardBIOS CMOS Setup Utility

Advanced Chipset Features

DRAM Timing Selectable	By SPD		Item Help
X CAS Latency Time	2.5		____________________________
X Active To Precharge Delay	7
X DRAM RAS# To CAS# Delay	3		Menu Level	¾
X DRAM RAS# Precharge	3
DRAM Data Integrity Mode	Non-ECC
MGM Core Frequency	Auto Max 266MHz
System BIOS Cacheable	Enabled
Video BIOS Cacheable	Disabled
Memory Hole At 15M-16M	Disabled
Delayed Transaction	Enabled
Delay Prior To Thermal	16Min.
AGP Aperture Size (MB)	64
** On-Chip VGA Setting **	Enabled
On-Chip VGA
On-Chip Frame Buffer Size	32MB
Boot Display	CRT
Panel Scaling	Auto
↑↓←→Move Enter: Select +/-/PU/PD: Value		F10: Save ESC: Exit		F1: General Help
F5: Previous Values F6: Fail-safe defaults		F7: Optimized Defaults

DRAM Timing Selectable:

Select the operating system that is selecting DRAM timing, so select SPD for setting SDRAM timing by SPD.

The choice: Manual, By SPD.

CAS Latency Time:

When synchronous DRAM is installed, the number of clock cycles of CAS latency depends on the DRAM timing.

The choice: 2, 2.5.

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