Intel I/O Processor, IQ80332 Getting Started 2

Evaluation Platform Board Manual 15

Getting Started 2

The 80332 is a software developme nt environment for IQ80332. Software updates and additional

offerings from vendors can change frequently. To keep up-to-date, please visit

http://www.intel-ioprocessortools.com/kshow case/view for the latest updates.

2.1 Kit Content

The 80332 Kit contains the following items:

•IQ80332 with 400MHz DDRII SDRAM DIMMs

•Code|Lab* Development Environment from Accelerated Technology Incorporated*

•JTAG Emulation uni t

•Serial Cable and RJ11 Adapter

2.2 Hardware Installation

Warni ng: Static charges can severely damage the boards. Be sure you are properly gro unde d before removi ng

the board from the anti-static bag.

2.2.1 First-Time Installation and Test

For first-time installation, vis ually inspect the 80332 for an y damage made during shipme nt. Follow

the host system manufacturer’s instructions for installing a PCI Express adapter card. The b oard is a

full-length host bus adapter card that requires a PCI Express slot free from obstructions. The IQ80332

has a x8 (read as ‘by eight’) edge connector.

Note: Please note, at this time the IQ80332 does NOT work in a passive backplane. This is due to the

nature of the PCI Express linking protocol. For the I/O processor to success f ully come out of reset,

a link must be established on the PCI Express bus. Without another device on a passive backplane

to ‘talk to’, a link is not established.

Contents

Main 2 September, 2005 Document Number: 274069003US Intel IQ80332 I/O Processor Evaluation Platform Board Manual Contents Page Page Figures Examples Revision History Introduction 1 1.1 Document Purpose and Scope 1.2 Other Related Documents Introduction 1.3 Electronic Information Tabl e 3 provides additional information on the m ajor components of 80332. 1.4 Component References Table 2. Electronic Information Table 3. Component Reference 1.5 Terms and Definitions 1.6 Intel 80332 I/O Processor Page Introduction 1.7 Intel IQ80332 I/O Processor Evaluation Platform Board Features Table 5. Summary of Features Getting Started 2 2.1 Kit Content 2.2 Hardware Installation 2.2.1 First-Time Installation and Test 2.2.2 Power Requirements 2.3 Factory Settings 2.4 Development Strategy 2.4.1 Supported Tool Buckets 2.4.2 Contents of the Flash 2.5 Target Monitors 2.5.1 RedHat RedBoot 2.6 Host Communications Examples 2.6.1 Serial-UART Communication 2.6.2 JTA G Debug Communication 2.6.3 Network Communication 2.6.4 GNUPro GDB/Insight Page Page Page Hardware Reference Section 3 3.1 Functional Diagram 8 MB Figure 5 shows the functional block for the 80332 . Figure 5. Functional Block Diagram StrataFLASH 3.2 Board Form-Factor/Connectivity DDR II DIMM Battery 107 Figure 6. Board Form Factor 3.3 Power 3.4 Memory Subsystem 3.4.1 DDR SDRAM 3.4.1.1 Battery Backup 3.4.2 Flash Memory Requirements 3.5 Interrupt Routing 3.6 Intel IQ80332 I/O Processor Evaluation Platform Board Peripheral Bus The 80332 populates the periph eral bus as depicted by Figure 7. Figure 7. Intel IQ80332 I/O Processor Evaluation Platform Board Peripheral Bus Topology Intel 8033 2 I/O Processor PBI Bus Table 10. Peripheral Bus Features 3.6.1 Flash ROM 3.6.2 UART 3.6.3 Non-Volatile RAM 3.6.4 Audio Buzzer 3.6.5 HEX Display 3.6.6 Rotary Switch 3.6.7 Battery Status Page 3.7.2 JTAG Debug The 80332 has a 20-pin JTAG connector (J7D2) th at is in compliant with ARM Multi-IC E guidelines. 3.7.2.1 JTAG Port Figure 9. JTAG Port Pin-ou t 3.8 Board Reset Scheme 82545EM Figure 10. RESET Sources DDR II SDRAM Intel 80332 I/O Processor PCI-X Con A 3.9 Switches and Jumpers 3.9.1 Switch Summary 3.9.2 Default Switch Settings of S7A1- Visual Table 15. Switch Summary Table 16. Switch S7A1 3.9.3 Jumper Summary 3.9.4 Connector Summary 3.9.5 General Purpose Input/Output Header Table 17. Jumper Summary Table 18. Connector Summary 3.9.6 Detail Descriptions of Switches/Jumpers 3.9.6.1 Switch S1C2: 80332 Reset 3.9.6.2 Switch S6A1: BPCI-X Reset 3.9.6.3 Switch S8A1: Rotary 3.9.6.4 Switch S7A1 Page Page 3.9.6.5 Jumper J7D1: Flash bit-width 3.9.6.6 Jumper J1C1: JTAG Chain 3.9.6.7 Jumper J1D2: UART Control 3.9.6.8 Jumper J7B4: SMBus Header 3.9.6.9 Jumper J9D3: Buzzer Volume Control Software Reference 4 4.1 DRAM 4.2 Components on the Peripheral Bus 4.2.1 Flash ROM Software Reference 4.2.2 Peripheral Bus Memory Map The Table 4 1 is the physical memory map o f the devices on the 80332 Peripher al Bus: Table 41. Peripheral Bus Memory Map Software Reference 4.3 Board Support Package (BSP) Examples 4.3.1 Intel 80332 I/O Processor Memory Map 4.3.2 RedBoot* Intel 80332 I/O Processor Memory Map 4.3.3 RedBoot Intel 80332 I/O Processor Files 4.3.4 RedBoot 80332 DDR Memory Initialization Sequence IQ80321 and IQ80332 Comparisons IQ80321 and IQ80332 Comparisons A Page Getting Started and Debugger B B.1 Introduction B.1.1 Purpose B.1.2 Necessary Hardware and Software B.1.3 Related Documents B.1.4 Related Web Sites B.2 Setup B.2.1 Hardware Setup B.2.2 Software Setup B.3 New Project Setup B.3.1 Creating a New Project B.3.2 Configuration File Project code|lab EDE Tools Help Edit View Build, Debug B.4 Flashing with JTAG B.4.1 Overview B.4.2 Using Flash Programmer B.5 Debugging Out of Flash B.6 Building an Executable File From Example Code B.7 Running the Code|Lab Debugger B.7.1 Launching and Configuring Debugge r B.7.2 Manually Loading and Executing an Application Program B.7.3 Displaying Source Code B.7.4 Using Breakpoints B.7.5 Stepping Through the Code B.7.6 Setting Code|Lab Debug Options B.8 Exploring the Code|Lab Debug Windows B.8.1 Toolbar Icons B.8.2 Workspace Window B.8.3 Source Code B.8.4 4 Debug and Console Windows B.8.6 Registers Window B.8.7 Watch Window B.8.8 Variables Window B.9 Debugging Basics B.9.1 Overview B.9.2 Hardware and Software Breakpoints B.9.2.1 Software Breakpoints B.9.2.2 Hardware Breakpoints B.9.3 C.9.3 Exceptions/Trapping