28 Evaluation Platform Board Manual
Intel® IQ80332 I/O Processor
Hardware Reference Section
3.4 Memory Subsystem
The Memory Controller of 80332 controls the DDR SDRAM memory subsystem. It features pro-
grammable chip selects and support for error correction codes (ECC). The memory cont roller can
be configured for DDR SDRAM at 333 MHz and DDR-II at 400 MHz. The memory controller
supports pipelined access and arbitrati on contro l to ma ximiz e performan ce. The memory cont roller
interface configuration support includes Unbuffered DIMMs, Registered DIMMs, and discrete
DDR SDRAM devices.
This IQ80332 has DDR-II at 400 MHz DIMM on the board. The memory subsystem o f the
evaluation board consists of the SDRAM as well as the Flash memo ry subsystems.

3.4.1 DDR SDRAM

The DDR SDRAM interface consists of a 64-bit w ide data path to support up to 3.2 Gbyt es/sec
throughput. An 8-bit Error Correction Cod e (ECC) is stored into the DDRII SDRAM ar ray along
with the data and is checked when the data is read.
The IQ80332 features on boar d registered DDRII 400 MHz S DRAM, arranged 512 M bit x16 in
density (256 MB), and w ith ECC.

3.4.1.1 Battery Backup

Battery backup is provided to save any informat ion in DDR during a power failure. The evalua tion
board contains a 4V Li-ion battery, a charging circuit and a regulator circuit.
DDRII technology provides enabling data preservation through t he self-refresh command. When the
processor receives an active Primary PCI-X reset, the self-refresh comman d issues, driving SCKE
signals low. Upon seeing this condition, the board logic circuit holds SCKE low before the processor
loses power. Batteries maintain power to DDRII an d logic, to ensure self-refresh mode. When the
circuit detects PRST# returning to inactive state, the circuit relea ses the hold on SCKE. Removing the
battery can disable the battery circuit. When the battery remains in the platform when it is de-powered
and/or removed from the chas sis, the battery maintains DDR II for about four hours. Once power is
reapplied, the battery is fully charged.
The CPLD contains information in regards to the battery status. Please see Section 3.6.7, “Battery
Status” on page 34 for more details.