Intel M570TU B.Schematic Diagrams, B - 4 Penryn 2/2, Sheet 3 of Penryn 2/2, Place Near Cpu

Schematic Diagrams

Penryn 2/2

B.Schematic Diagrams

Sheet 3 of 42

Penryn 2/2

V C OR E

U 2 6

C

V C O R E

A 4

U 2 6 D

P 6

V S S [ 0 0 1 ]

V S S

[ 08 2 ]

A 7

A B 2 0

A

8

P 21

A 9

V C C [ 00 1 ]

V C C [ 0 68 ]

A B 7

A 1 1

V S S [ 0 0 2 ]

V S S

[ 08 3 ]

P 24

A 1 0

V C C [ 00 2 ]

V C C [ 0 69 ]

A C 7

V D D 3

A 1 4

V S S [ 0 0 3 ]

V S S

[ 08 4 ]

R 2

A 1 2

V C

C [ 00 3 ]

V C C [ 0 70 ]

A C 9

3/12_Cost

down

A 1 6

V S S [ 0 0 4 ]

V S S

[ 08 5 ]

R 5

PLACE NEAR CPU

V C

C [

00 4 ]

V C C [ 0 71 ]

V S S [ 0 0 5 ]

V S S

[ 08 6 ]

A 1 3

V C

C [

00 5 ]

V C C [ 0 72 ]

A C 1 2

A 1 9

V S S [ 0 0 6 ]

V S S

[ 08 7 ]

R 2 2

V C O R E

A 1 5

V C C [ 00 6 ]

V C C [ 0 73 ]

A C 1 3

R 4 4 1

A 2 3

V S S [ 0 0 7 ]

V S S

[ 08 8 ]

R 2 5

A 1 7

A C 1 5

A F 2

T 1

A 1 8

V C C [ 00 7 ]

V C C [ 0 74 ]

A C 1 7

* 1 K _ 1% _ 0 4

B 6

V S S [ 0 0 8 ]

V S S

[ 08 9 ]

T 4

A 2 0

V C C [ 00 8 ]

V C C [ 0 75 ]

A C 1 8

B

8

V S S [ 0 0 9 ]

V S S

[ 09 0 ]

T 2 3

B 7

V C C [ 00 9 ]

V C C [ 0 76 ]

A D 7

B 1 1

V S S [ 0 1 0 ]

V S S

[ 09 1 ]

T 2 6

C 5 9 7

C 5 9 6

C 59 5

C 5 9 4

C 13 9

C 5 9 3

C 5 92

C 5 7 2

C 8 6

C 7 6

B 9

V C

C [ 01 0 ]

V C C [ 0 77 ]

A D 9

B 1 3

V S S [ 0 1 1 ]

V S S

[ 09 2 ]

U 3

B 1 0

V C C [ 01 1 ]

V C C [ 0 78 ]

A D 1 0

C P U _ T MP _ S E N 2 2

B 1 6

V S S [ 0 1 2 ]

V S S

[ 09 3 ]

U 6

1 0U _ 10 V _ 0 8 *1 0 U _ 1 0 V _ 08 1 0 U _ 1 0 V _ 08 * 10 U _ 10 V _ 0 8 *1 0 U _1 0 V _ 0 8 1 0 U _ 1 0 V _ 0 8 1 0 U _1 0 V _ 0 8 10 U _ 10 V _ 0 8 10 U _ 10 V _ 0 8 10 U _1 0 V _ 0 8

B 1 2

V C C [ 01 2 ]

V C C [ 0 79 ]

A D 1 2

B 1 9

V S S [ 0 1 3 ]

V S S

[ 09 4 ]

U 2 1

V C

C [ 01 3 ]

V C C [ 0 80 ]

V S S [ 0 1 4 ]

V S S

[ 09 5 ]

B 1 4

A D 1 4

T R 1

B 2 1

U 2 4

B 1 5

V C C [ 01 4 ]

V C C [ 0 81 ]

A D 1 5

*1 0 K (0 6 0 3)

B 2 4

V S S [ 0 1 5 ]

V S S

[ 09 6 ]

V 2

B 1 7

V C

C [ 01 5 ]

V C C [ 0 82 ]

A D 1 7

C 5

V S S [ 0 1 6 ]

V S S

[ 09 7 ]

V 5

V C OR E

V C C [ 01 6 ]

V C C [ 0 83 ]

V S S [ 0 1 7 ]

V S S

[ 09 8 ]

B 1 8

A D 1 8

C

8

V 22

B 2 0

V C

C [ 01 7 ]

V C C [ 0 84 ]

A E 9

C 1 1

V S S [ 0 1 8 ]

V S S

[ 09 9 ]

V 25

C 9

V C C [ 01 8 ]

V C C [ 0 85 ]

A E 1 0

C 1 4

V S S [ 0 1 9 ]

V S S

[ 10 0 ]

W 1

C 1 0

V C C [ 01 9 ]

V C C [ 0 86 ]

A E 1 2

C 1 6

V S S [ 0 2 0 ]

V S S

[ 10 1 ]

W 4

C 5 4 8

C 5 7 1

C 55 3

C 5 4 7

C 56 8

C 5 6 9

C 5 52

C 5 5 1

C 5 5 0

C 5 4 9

C 1 2

V C

C [ 02 0 ]

V C C [ 0 87 ]

A E 1 3

C 1 9

V S S [ 0 2 1 ]

V S S

[ 10 2 ]

W 23

C 1 3

V C C [ 02 1 ]

V C C [ 0 88 ]

A E 1 5

C

2

V S S [ 0 2 2 ]

V S S

[ 10 3 ]

W 26

* 2 2 U _ 6 . 3V _0 8 22 U _ 6. 3 V _ 0 8 2 2U _ 6 . 3V _0 8 2 2 U _6 . 3 V _ 0 8 2 2 U _ 6 . 3 V _ 08 22 U _6 . 3 V _ 0 8 * 2 2 U _ 6 . 3V _0 8 2 2 U _ 6 . 3 V _ 08 2 2U _ 6 . 3V _0 8

2 2U _ 6 . 3V _0 8

C 1 5

V C C [ 02 2 ]

V C C [ 0 89 ]

A E 1 7

C 2 2

V S S [ 0 2 3 ]

V S S

[ 10 4 ]

Y 3

C 1 7

V C C [ 02 3 ]

V C C [ 0 90 ]

A E 1 8

C 2 5

V S S [ 0 2 4 ]

V S S

[ 10 5 ]

Y 6

C 1 8

V C C [ 02 4 ]

V C C [ 0 91 ]

A E 2 0

D 1

V S S [ 0 2 5 ]

V S S

[ 10 6 ]

Y 2 1

D 9

V C

C [ 02 5 ]

V C C [ 0 92 ]

A F 9

D 4

V S S [ 0 2 6 ]

V S S

[ 10 7 ]

Y 2 4

V C O R E

D 1 0

V C C [ 02 6 ]

V C C [ 0 93 ]

A F 1 0

1. 05 V S

R S V D _ D 8

D

8

V S S [ 0 2 7 ]

V S S

[ 10 8 ]

A A 2

D 1 2

V C

C [ 02 7 ]

V C C [ 0 94 ]

A F 1 2

3/12_Cost down

D 1 1

V S S [ 0 2 8 ]

V S S

[ 10 9 ]

A A 5

V C C [ 02 8 ]

V C C [ 0 95 ]

V S S [ 0 2 9 ]

V S S

[ 11 0 ]

R S V D _ A A 8

D 1 4

A F 1 4

D 1 3

A A 8

D 1 5

V C C [ 02 9 ]

V C C [ 0 96 ]

A F 1 5

2008/1/15

1

D 1 6

V S S [ 0 3 0 ]

V S S

[ 11 1 ]

A A 11

C 9 9

C 9 2

C 83

C 7 7

C 95

C 8 9

C 5 6 7

D 1 7

V C

C [

03 0 ]

V C C [ 0 97 ]

A F 1 7

1. 0 5 V S _ V C C P

L 3 9

D 1 9

V S S [ 0 3 1 ]

V S S

[ 11 2 ]

A

A 14

+

D 1 8

V C

C [

03 1 ]

V C C [ 0 98 ]

A F 1 8

DVT

0 _ 0 6

D 2 3

V S S [ 0 3 2 ]

V S S

[ 11 3 ]

A

A 16

1 u_ 6 . 3 V _ 0 4

*1 u _ 6 . 3 V _0 4

1u _ 6 . 3 V _ 04

1 u _ 6. 3 V _ 0 4

1 u _6 . 3 V _ 0 4

* 1 u_ 6 . 3 V _ 0 4

E 7

V C

C [ 03 2 ]

V C C [ 0 99 ]

A F 2 0

D 2 6

V S S [ 0 3 3 ]

V S S

[ 11 4 ]

A A 19

3 3 0 u _2 V _ D

E 9

V C

C [ 03 3 ]

V C C [ 1 00 ]

E

3

V S S [ 0 3 4 ]

V S S

[ 11 5 ]

A A 22

V C

C [ 03 4 ]

2

V S S [ 0 3 5 ]

V S S

[ 11 6 ]

V C OR E

E 1 0

V C C [ 03 5 ]

V C C P [ 01 ]

G2 1

E 6

V S S [ 0 3 6 ]

V S S

[ 11 7 ]

A A 25

V C O R E

E 1 2

V 6

E

8

A B 1

E 1 3

V C C [ 03 6 ]

V C C P [ 02 ]

J6

E 1 1

V S S [ 0 3 7 ]

V S S

[ 11 8 ]

A B 4

E 1 5

V C C [ 03 7 ]

V C C P [ 03 ]

K 6

C 5 7 3

E 1 4

V S S [ 0 3 8 ]

V S S

[ 11 9 ]

A B 8

C 3 4

C 36

E 1 7

V C C [ 03 8 ]

V C C P [ 04 ]

M6

+

E 1 6

V S S [ 0 3 9 ]

V S S

[ 12 0 ]

A B 11

E 1 8

V C C [ 03 9 ]

V C C P [ 05 ]

J2 1

E 1 9

V S S [ 0 4 0 ]

V S S

[ 12 1 ]

A B 13

C 8 4

C 7 4

C 75

C 9 4

C 66

C 8 5

0 . 0 1 u _5 0 V _ 0 4

0. 0 1 u _ 50 V _ 0 4

V C C [ 04 0 ]

V C C P [ 06 ]

2A; 80mils

1 50 u _ 4 V _ B

V S S [ 0 4 1 ]

V S S

[ 12 2 ]

E 2 0

K 2 1

E 2 1

A B 16

F 7

V C C [

04 1 ]

V C C P [ 07 ]

M2 1

E 2 4

V S S [ 0 4 2 ]

V S S

[ 12 3 ]

A

B 19

*1 u _ 6. 3V _ 0 4 1 u _6 . 3 V _ 0 4

1 u _6 . 3 V _ 0 4

1u _ 6 . 3 V _ 04

1 u _6 . 3 V _ 0 4

1 u _ 6. 3V _0 4

F 9

V C C [ 04 2 ]

V C C P [ 08 ]

N 2 1

F

5

V S S [ 0 4 3 ]

V S S

[ 12 4 ]

A B 23

F 1 0

V C C [ 04 3 ]

V C C P [ 09 ]

N 6

G TL R E F 2 _ C T R L

F 8

V S S [ 0 4 4 ]

V S S

[ 12 5 ]

A B 26

F 1 2

V C C [ 04 4 ]

V C C P [ 10 ]

R 2 1

1 . 5V S

F 1 1

V S S [ 0 4 5 ]

V S S

[ 12 6 ]

A C 3

V C OR E

EMI

F 1 4

V C C [

04 5 ]

V C C P [ 11 ]

R 6

20mils

Layout note:

F 1 3

V S S [ 0 4 6 ]

V S S

[ 12 7 ]

A

C 6

V C O R E

F 1 5

V C C [

04 6 ]

V C C P [ 12 ]

T2 1

F 1 6

V S S [ 0 4 7 ]

V S S

[ 12 8 ]

A

C 8

R S V D _ A C 8

F 1 7

V C C [

04 7 ]

V C C P [ 13 ]

T6

C 5 4 4

C

F 1 9

V S S [ 0 4 8 ]

V S S

[ 12 9 ]

A

C 1 1

C 3 2

C 37

F 1 8

V C C [

04 8 ]

V C C P [ 14 ]

V 2 1

54Near2

pin B26,C26

F

2

V S S [ 0 4 9 ]

V S S

[ 13 0 ]

A

C 1 4

F 2 0

V C C [ 04 9 ]

V C C P [ 15 ]

W 2 1

F 2 2

V S S [ 0 5 0 ]

V S S

[ 13 1 ]

A C 1 6

C 3 8

C 33

C 3 5

C 1 02

C 7 3

C 6 5

B R 1#

A A 7

V C C [ 05 0 ]

V C C P [ 16 ]

1 0 U _ 1 0 V _0 8

0 . 0 1 u_ 5 0 V _ 04

F 2 5

V S S [ 0 5 1 ]

V S S

[ 13 2 ]

A C 1 9

0 . 0 1 u _5 0 V _ 0 4

0 . 0 1 u_ 5 0 V _ 0 4

A A 9

V C C [ 05 1 ]

B 2 6

G 4

V S S [ 0 5 2 ]

V S S

[ 13 3 ]

A C 2 1

*0 . 0 1 u _5 0 V _ 0 4 * 0. 1 u _ 1 0V _0 4

* 0. 1u _ 1 0 V _0 4

0 . 1 u _ 10 V _ 0 4

*0 . 1 u_ 1 0 V _ 0 4

0. 1u _ 1 0 V _0 4

V C C [ 05 2 ]

V C C A [ 01 ]

V S S [ 0 5 3 ]

V S S

[ 13 4 ]

A A 1 0

C 2 6

G 1

A C 2 4

V C C [ 05 3 ]

V C C A [ 02 ]

V S S [ 0 5 4 ]

V S S

[ 13 5 ]

A A 1 2

G 2 3

A D 2

A A 1 3

V C C [ 05 4 ]

A D 6

H _ V I D 0

3 5

G 2 6

V S S [ 0 5 5 ]

V S S

[ 13 6 ]

A D 5

V C C [ 05 5 ]

V I D [ 0 ]

V S S [ 0 5 6 ]

V S S

[ 13 7 ]

A A 1 5

A F 5

H _ V I D 1

3 5

H 3

A D 8

A A 1 7

V C C [ 05 6 ]

V I D [ 1 ]

A E 5

H 6

V S S [ 0 5 7 ]

V S S

[ 13 8 ]

A D 1 1

A A 1 8

V C C [ 05 7 ]

V I D [ 2 ]

A F 4

H _ V I D 2

3 5

H 2 1

V S S [ 0 5 8 ]

V S S

[ 13 9 ]

A D 1 3

A A 2 0

V C C [ 05 8 ]

V I D [ 3 ]

A E 3

H _ V I D 3

3 5

H 2 4

V S S [ 0 5 9 ]

V S S

[ 14 0 ]

A D 1 6

A B 9

V C C [ 05 9 ]

V I D [ 4 ]

A F 3

H _ V I D 4

3 5

J 2

V S S [ 0 6 0 ]

V S S

[ 14 1 ]

A D 1 9

V C C [ 06 0 ]

V I D [ 5 ]

H _ V I D 5

3 5

V S S [ 0 6 1 ]

V S S

[ 14 2 ]

A C 1 0

A E 2

H _ V I D 6

3 5

J 5

A D 2 2

A B 1 0

V C C [ 06 1 ]

V I D [ 6 ]

J 2 2

V S S [ 0 6 2 ]

V S S

[ 14 3 ]

A D 2 5

1 . 0 5 V S _ V C C P

A B 1 2

V C C [ 06 2 ]

J 2 5

V S S [ 0 6 3 ]

V S S

[ 14 4 ]

A E 1

A B 1 4

V C C [ 06 3 ]

V C C S E N S E

A F 7

V C C S E N S E

V C C S E N S E 3 5

K 1

V S S [ 0 6 4 ]

V S S

[ 14 5 ]

A E 4

A B 1 5

V C C [ 06 4 ]

K 4

V S S [ 0 6 5 ]

V S S

[ 14 6 ]

A E 8

H _ B P M 2_ 3 #

V C C [ 06 5 ]

V S S [ 0 6 6 ]

V S S

[ 14 7 ]

C 5 5 8

C 6 9

C 62

C 71

C 7 8

C 9 6

A B 1 7

K 2 3

A E 11

A B 1 8

V C C [ 06 6 ]

V S S S E N S E

A E 7

V S S S E N S E

V S S S E N S E 3 5

K 2 6

V S S [ 0 6 7 ]

V S S

[ 14 8 ]

A E 14

+

0 . 1 u_ 1 0 V _ 04

0 . 1 u_ 1 0 V _ 0 4

0 . 1 u _1 0 V _ 0 4

0 . 1 u _ 10 V _ 0 4

0 . 0 1 u _ 50 V _ 0 4

V C C [ 06 7 ]

L 3

V S S [ 0 6 8 ]

V S S

[ 14 9 ]

A E 16

* 47 0 u _ 2. 5V _D

P en ry n

L 6

V S S [ 0 6 9 ]

V S S

[ 15 0 ]

A E 19

R 4 6 0

R 4 59

Layout note:

L 2 1

V S S [ 0 7 0 ]

V S S

[ 15 1 ]

A E 23

L 2 4

V S S [ 0 7 1 ]

V S S

[ 15 2 ]

A E 26

M 2

V S S [ 0 7 2 ]

V S S

[ 15 3 ]

A

2

1 . 0 5 V S _ V C C P

V C O R E

1 0 0_ 1 % _ 04

1 0 0 _1 % _ 0 4

Route VCCSENSE and

M 5

V S S [ 0 7 3 ]

V S S

[ 15 4 ]

A F 6

M 2 2

V S S [ 0 7 4 ]

V S S

[ 15 5 ]

A

F 8

VSSSENSE traces at 27.4Ohm

M 2 5

V S S [ 0 7 5 ]

V S S

[ 15 6 ]

A

F 11

with 50 mil spacing.

N 1

V S S [ 0 7 6 ]

V S S

[ 15 7 ]

A

F 13

C 8 2

C 8 8

C 93

C 90

C 8 1

V S S [ 0 7 7 ]

V S S

[ 15 8 ]

Place PU and PD within 1

N 4

V S S [ 0 7 8 ]

V S S

[ 15 9 ]

A F 16

0. 1u _ 1 0 V _ 04

0 . 1 u_ 1 0 V _ 04

0 . 1 u_ 1 0 V _ 0 4

0 . 0 1 u_ 5 0 V _ 0 4

0 . 0 1 u _5 0 V _ 0 4

N 2 3

A

F 19

inch of CPU.

N 2 6

V S S [ 0 7 9 ]

V S S

[ 16 0 ]

A

F 21

P 3

V S S [ 0 8 0 ]

V S S

[ 16 1 ]

A 25

V S S [ 0 8 1 ]

V S S

[ 16 2 ]

A F 25

V S S

[ 16 3 ]

+VCCP = 1.05V (0.997V~1.102V)

P e n ry n

V _ T H R M

Quad Core CPU Thermal

1 . 05 V S

3/12_Cost

down

1

U 2

4

2

H _ T D O _ M

R 44 3

*0 _ 04

Z 0 30 8

V D D

T H E R M

V _ T H R M_ R

2 , 15 , 2 2

IC.

3 . 3 V S

1 . 05 V S

2

H _ T D I _M

R 43 9

*0 _ 04

R 4 35

*5 4 . 9_ 1 % _ 0 4

2

H _ T H R MD A _ 2

R 1 1 6

*0 _ 0 4

Z 0 30 2 2

6

D +

A LE R T

P M _T H R M # _R 2

2 , 4 , 1 3 , 2 2, 2 3 , 2 4 , 2 9, 3 3 , 3 4 , 3 7, 3 8 V D D 3

C 1 4 1

C 1 4 8

1 . 05 V S

C P U _ GT L R E F 2

V C O R E 2 , 5 , 9 , 1 2, 1 3 , 1 4 , 1 5, 1 6 , 1 9 , 2 0, 2 1 , 2 2 , 2 3, 2 4 , 2 5 , 2 8, 3 0 , 3 3 , 3 5, 3 7 3 . 3 V S

*1 0 u _1 0 V _ 0 8

*1 0 0 0 p_ 5 0 V _ 04

Z 0 30 3 3

7

R 2 8

R 3 4

S MD _ TH E R M 2 , 2 2

*1 0 K _ 0 4

9, 1 3 , 1 4 , 1 6, 2 1 , 2 3 , 3 1, 3 6 1 . 5 V S

R 1 2 1

*0 _ 0 4

5

D -

S D A T A

8

*1 K _ 1 % _ 04

2 , 4 , 9, 1 3 , 1 6 , 2 3, 3 2 1 . 0 5 V S

2

H _ T H R MD C _2

GN D

S C L K

S MC _ TH E R M 2 , 2 2

R 2 3

B R 1 #

R 12 0

*0 _ 04

3 5

V C OR E

*a S C 7 5 25

*1 0 K _ 0 4

Z 0 3 07

H _ B P M 2 _3 #

D

R 11 7

*0 _ 04

C

Layout Note:

Layout Note:

G T L R E F 2 _ C T R L

Z 0 30 6 B

R 3 3

R S V D _ A C 8

R 11 8

*0 _ 04

EQ9

G

Q8

1000p Near to

Route H_THRMDA_2 and

R 24

*1 0 K _ 04

*2 N 39

0 4

S

*2 N 70 0 2

*2 K _ 1 % _ 04

R S V D _ A A 8

R 11 9

*0 _ 04

Thermal IC

H_THERMDC on same layer.

R S V D _ D 8

R 53

*0 _ 04

10 mil trace on 10 mil

GT L R E F 2_ C T R L

R 54

*0 _ 04

spacing.

B - 4 Penryn 2/2