BIOS SETUP
MB893 User’s Manual 35
This Setup menu controls the configuration of the chipset.
Phoenix - AwardBIOS CMOS Setup Utility
Advanced Chipset Features
DRAM Timing Selectable By SPD ITEM HELP
CAS Latency Time Auto Menu Level
DRAM RAS# to CAS# Delay Auto
DRAM RAS# Precharge Auto
Precharge Delay Auto
SLP_S4# Assertion Width
System Memory Frequency Auto
System BIOS Cacheable Enabled
Video BIOS Cacheable Enabled
Memory Hole at 15M-16M Disabled
PCI Express Root Press Enter
On-Chip Video Memory Press Enter
On-Chip Frame Buffer Size
Memory 8MB
DVMT Version DVMT 3.0
FIXED Memory Size 64MB
DVMT Memory Size 64MB
Boot Display Auto
DRAM Timing Selectable
This option refers to the method by which the DRAM timing is selected.
The default is By SPD.
CAS Latency Time
You can configure CAS latency time in HCLKs as 2 or 2.5 or 3. The
system board designer should set the values in this field, depending on
the DRAM installed. Do not change the values in this field unless you
change specifications of the installed DRAM or the installed CPU.
DRAM RAS# to CAS# Delay
This option allows you to insert a delay between the RAS (Row Address
Strobe) and CAS (Column Address Strobe) signals. This delay occurs
when the SDRAM is written to, read from or refreshed. Reducing the
delay improves the performance of the SDRAM.
DRAM RAS# Precharge
This option sets the number of cycles required for the RAS to
accumulate its charge before the SDRAM refreshes. The default setting
for the Active to Precharge Delay is Auto.
Precharge Delay
The default setting for the Precharge Delay is Auto.