CV-L105
7.2. Configuration via I/F connector and jumpers
The binning function, pixel rate and
Below table describe the possible states of these inputs. Please refer to fig. 7. for principle.
Function
| Binning |
| Clock | ||||||
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| Pin |
| Pin |
JP3 | JP4 | #30 | JP1 |
| JP2 |
| #10 | JP5 | #31 |
Remarks
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| O |
| S |
| H |
| O |
| O |
| H |
| O |
| H | Factory setting. | |||||||||
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| S |
| O |
| L |
| O |
| O |
| H |
| O |
| H | #30 low for | ||||||||||
| by I/F pin #30 |
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| H |
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| #30 high for | ||||||||||||||||
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| Binning fixed at 1024 by JP2 |
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| S |
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| O |
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| H |
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| O |
| S |
| H |
| x |
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| H |
| JP2 closed for 1024 | ||||
| Binning select by I/F pin #10 |
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| S |
| O |
| H |
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| #10 high for 2048 | |||||||||
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| disabled | |||||
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| L |
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| #10 low for 1024 | |||||||||
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| Pixel clock select by JP5 |
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| O |
| H | JP5 open for 30 MHz | Set by | ||
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| S |
| JP5 closed for 15 MHz | |||||
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| S |
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| O |
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| H |
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| x |
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| x |
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| H |
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| jumper | |||
| Pixel clock select by I/F pin |
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| O |
| H | #31 high for 30 MHz | & pin | ||||||||
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| #31 |
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| L | #31 low for 15 MHz |
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| O = jumper open |
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| S = jumper short |
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H = input high. ( open. 5V by the internal 4.7 kΩ
x = do not care
7.3. Potentiometers and jumpers placing
There are 5 solder jumpers on the main board (PK8234B), which are accessible for the user. On the board (PK8235B) 7 potentiometers are found. The top one marked A/D is for factory adjustment. Do not touch it.
The red, green and blue gain and offset potentiometers is factory adjusted to white color balance at 3100K. It is used in factory setting configuration. As the green gain and offset is reference, do not touch it.
JP4 JP5 JP2 P1 JP3
Top
A/D offset
R gain
R offset
G gain
G offset
B gain
B offset
Fig. 21. Potentiometers and jumpers placing
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