)

Table 3.3 PCI Connector J1 (Back)1

Signal Name

Pin

Signal Name

Pin

 

 

 

 

TRST2

1

AD16

32

+12 V

2

+3.3 V

33

TMS

3

FRAME2

34

TDI

4

GND

35

 

 

 

 

+5 V

5

TRDY2

36

INTA2

6

GND

37

INTC2

7

STOP2

38

+5 V

8

+3.3 V

39

 

 

 

 

RESERVED

9

SDONE

40

3 V/5 V

10

SBO2

41

RESERVED

11

GND

42

KEYWAY

12

PAR

43

 

 

 

 

KEYWAY

13

AD15

44

 

 

 

 

RESERVED

14

+3.3 V

45

RST2

15

AD13

46

3 V/5 V

16

AD11

47

 

 

 

 

GNT2

17

GND

48

GND

18

AD09

49

 

 

 

 

RESERVED

19

KEYWAY

50

AD30

20

KEYWAY

51

 

 

 

 

+3.3 V

21

C_BE02

52

AD28

22

+3.3 V

53

 

 

 

 

AD26

23

AD06

54

 

 

 

 

GND

24

AD04

55

 

 

 

 

AD24

25

GND

56

 

 

 

 

IDSEL

26

AD02

57

 

 

 

 

+3.3 V

27

AD00

58

 

 

 

 

AD22

28

3 V/5 V

59

 

 

 

 

AD20

29

REQ642

60

GND

30

+5 V

61

 

 

 

 

AD18

31

+5 V

62

 

 

 

 

1.Shaded lines are not connected.

2.Active LOW signal.

3-6

Technical Specifications

Copyright © 2001 by LSI Logic Corporation. All rights reserved.