Bus Mastering

A high-performance way to transfer data. The host adapter controls the

 

transfer of data directly to and from system memory without interrupting

 

the computer’s microprocessor. This is the fastest way for multitasking

 

operating systems to transfer data.

Byte

A unit of information consisting of eight bits.

CISPR

A special international committee on radio interference (Committee,

 

International and Special, for Protection in Radio).

Configuration

Refers to the way a computer is setup; the combined hardware

 

components (computer, monitor, keyboard, and peripheral devices) that

 

make up a computer system; or the software settings that allow the

 

hardware components to communicate with each other.

CRC

Cyclic Redundancy Check is an error detection code used in Ultra160

 

SCSI. Four bytes are transferred with the data to increase the reliability

 

of data transfers. CRC is used on the Double Transition (DT) Data-In and

 

DT Data-Out phases.

CPU

Central Processing Unit. The “brain” of the computer that performs the

 

actual computations. The term Microprocessor Unit (MPU) is also used.

DMA Bus

A feature that allows a peripheral to control the flow of data to and from

Master

system memory by blocks, as opposed to PIO (Programmed I/O) where

 

the processor is in control and the flow is by byte.

Device Driver

A program that allows a microprocessor (through the operating system)

 

to direct the operation of a peripheral device.

Differential SCSI

A hardware configuration for connecting SCSI devices. It uses a pair of

 

lines for each signal transfer (as opposed to Single-Ended SCSI which

 

references each SCSI signal to a common ground).

DMI

Desktop Management Interface.

Domain

Domain Validation is a software procedure in which a host queries a

Validation

device to determine its ability to communicate at the negotiated Ultra160

 

data rate.

Double

In DT Clocking data is sampled on both the asserting and deasserting

Transition (DT)

edge of the REQ/ACK signal. DT Clocking may only be implemented on

Clocking

an LVD SCSI bus.

A-2

Glossary of Terms and Abbreviations

Copyright © 2001 by LSI Logic Corporation. All rights reserved.