Maxtor 52049H3, 51536H2, 53073H4, 546106 specifications DMATiming, Imin G Paramet ERS Mode

AT INTERFACE DESCRIPTION

DMATiming

T IMIN G PARAMET ERS

MODE 0

MODE 1

MODE 2

t0

Cycle Time (min)

480 ns

150 ns

120 ns

tC

DMAC K to DMARQ delay

tD

DIOR-/D IOW- (min)

215

ns

80 ns

70 ns

tE

DIOR- data access (min)

150

ns

60

ns

tF

DIOR- data hold (min)

5 ns

5 ns

5 ns

tG

DIOR-/DIOW- data setup (min)

100

ns

30 ns

20 ns

tH

DIOW- data hold (min)

20 ns

15

ns

10

ns

tI

DM AC K to DIOR-/D IOW - setup (min)

0

0

0

tJ

DIOR-/DIOW- to DMAC K hold (min)

20 ns

5 ns

5 ns

tKr

DIOR- negated puls e width (min)

50 ns

50

ns

25

ns

tKw

D IOW - negated puls e width (min)

215

ns

50

ns

25

ns

tLr

DIOR- to D MARQ delay (max)

120

ns

40 ns

35 ns

tLw

DIOW- to D MARQ delay (max)

40 ns

40 ns

35 ns

tZ

DMAC K- to tristate (max)

20 ns

25

ns

25

ns

Figure 5 - 3

Multi-word DMA Data Transfer

5 – 4