Ultra DMA Timing, Mode MIN MAX | Maxtor 6800 instruction

AT INTERFACE DESCRIPTION

Ultra DMA Timing

TIMING PARAMETERS (all times in nanoseconds)		MODE 0		MODE 1		MODE 2

		MIN	MAX	MIN	MAX	MIN	MAX

tCYC	Cycle Time (from STROBE edge to STROBE edge)	114		75		55
t2CYC	Two cycle time (from rising edge to next rising edge or	235		156		117
	from falling edge to next falling edge of STROBE)
tDS	Data setup time (at recipient)	15		10		7	70
tDH	Data hold time (at recipient)	5		5		5
tDVS	Data valid setup time at sender (time from data bus being	70		48		34	5
	valid until STROBE edge)
tDVH	Data valid hold time at sender (time from STROBE edge	6		6		6	20
	until data may go invalid)
tFS	First STROBE (time for device to send first STROBE)	0	230	0	200	0	170
tLI	Limited interlock time (time allowed between an action by	0	150	0	150	0	150
	one agent, either host or device, and the following action	0	150	0	150	0	150
	by the other agent)
tMLI	Interlock time with minimum	20		20		20
tUI	Unlimited interlock time	0		0		0
tAZ	Maximum time allowed for outputs to release		10		10		10
tZAH	Minimum delay time required for output drivers turning on	20		20		20
tZAD	(from released state)	0		0		0
tZAD		0		0		0
tENV	Envelope time (all control signal transitions are within the	20	70	20	70	20	70
	DMACK envelope by this much time)
tSR	STROBE to DMARDY (response time to ensure the		50		30		20
	synchronous pause case when the recipient is pausing)
tRFS	Ready-to-final-STROBE time (no more STROBE edges may		75		60		50
	be sent this long after receiving DMARDY- negation)
tRP	Ready-to-pause time (time until a recipient may assume	160		125		100
	that the sender has paused after negation of DMARDY-)
tIORDYZ	Pull-up time before allowing IORDY to be released		20		20		20
tZIORDY	Minimum time device shall wait before driving IORDY	0		0		0
tACK	Setup and hold times before assertion and negation of	20		20		20
	DMACK-
tSS	Time from STROBE edge to STOP assertion when the	50		50		50
	sender is stopping

DMARQ
(device)
tUI
DMACK-
(host)
tACK	tENV
STOP
(host)
tACK	tENV
HDMARDY-
(host)
tZIORDY
DSTROBE
(device)
tAZ
DD(15:0)
tACK
DA0, DA1, DA2,
CS0-, CS1-

tFS

tZAD
tFS
tZAD
tVDS	tDVH

Figure 5 - 4

Initiating an Ultra DMA Data In Burst

5 – 5

Image 36

Maxtor 6800 manual Ultra DMA Timing, Mode MIN MAX

Contents

HA RD Drive Produc T MA Nual DiamondMax Before You Begin U T I O N Contents Product Specifications Handling and Installation AT Interface Description Host Software Interface Interface Commands Service and SupportGlossary Figures Introduction Maxtor CorporationManual Organization Abbreviations Signal Conventions ConventionsKey Words Numbering DiamondMax 6800 Key Features Product Description Product Features Functional / Interface On-the-Fly Hardware Error Correction Code ECC Logical Block AddressingDefect Management Zone DMZ Software ECC Correction Read-Ahead Mode Cache ManagementBuffer Segmentation Automatic Write Reallocation AWR Major HDA Components Subsystem Configuration Jumper Location/ConfigurationCylinder Limitation Dual Drive Support Product Specifications Drive ConfigurationPerformance Specifications Models and Capacities Physical Dimensions Parameter Standard Metric Power Requirements Power Mode DefinitionsEPA Energy Star Compliance Environmental Limits Reliability Specifications Shock and Vibration Safety Regulatory Compliance Radiated Electromagnetic Field Emissions EMC ComplianceCanadian Emissions Statement Handling and Installation Hard Drive Handling PrecautionsPre-formatted Drive Important Notice Unpacking and Inspection Multi-pack Shipping Container Physical Installation Recommended Mounting ConfigurationRepacking Handling Precautions Tools for InstallationSystem Requirements Drive Identification Information General Requirements Hard Drive Identification Systems Using Cable Select Installing 5.25-inch Mounting Brackets and RailsInstalling in a Device Bay Mounting Drive in System Attaching Interface and Power Cables Attaching System Cables System Setup Setting the Bios CmosBios Cmos Parameters Hard Drive Preparation System Hangs During Boot Interface Connector AT Interface DescriptionPin Description Summary PIN Name Signal Name Signal Description Pin Description Table Timing Parameters Mode PIO Timing DMA Timing Mode MIN MAX Ultra DMA Timing Sustained Ultra DMA Data In Burst Device Terminating an Ultra DMA Data In Burst Initiating an Ultra DMA Data Out Burst Device Pausing an Ultra DMA Data Out Burst Device Terminating an Ultra DMA Data Out Burst Error Register Features RegisterHost Software Interface Task File Registers Sector Count Register Sector Number RegisterCylinder Number Registers Device/Head Register Command Register Command Name Command Code Parameters Used SDH Summary Control Diagnostic Registers Alternate Status RegisterDevice Control Register Digital Input Register Reset and Interrupt Handling Reset HandlingInterrupt Handling Interface Commands Set Feature Commands Read Commands Read SectorsRead Verify Sectors Read DMA Read Multiple Write Commands Set Multiple ModeWrite Sectors Write Verify Sectors Write Multiple Write DMA Set Feature Commands Set Features Mode Power Mode Commands Sleep Mode Initialization Commands Identify Drive 15-8 = PIO data transfer mode = Write Cache enabled Initialize Drive Parameters Seek, Format and Diagnostic Commands Execute Drive DiagnosticFormat Track A.R.T. Command Set Execute S.M.A.R.T Service and Support Service PolicyNo Quibble Service Support MaxFax Service Customer ServiceInternet Access Time Glossary Cylinder Zero Gigabyte GB Logical Block Addressing Read Gate Signal THIN-FILM Media