AT INTERFACE DESCRIPTION
Pin Description Table
PIN NAME | PIN | I/O | SIGNAL NAME | SIGNAL DESCRIPTION |
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RESET - | 01 | I | Host Reset | Reset signal from the host system. Active during power up and inactive after. |
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DD0 | 17 | I/O | Host Data Bus | 16 bit |
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| register and ECC byte transfers. All 16 bits used for data transfers. |
DD1 | 15 | I/O |
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DD2 | 13 | I/O |
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DD3 | 11 | I/O |
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DD4 | 09 | I/O |
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DD5 | 07 | I/O |
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DD6 | 05 | I/O |
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DD7 | 03 | I/O |
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DD8 | 04 | I/O |
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DD9 | 06 | I/O |
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DD10 | 08 | I/O |
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DD11 | 10 | I/O |
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DD12 | 12 | I/O |
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DD13 | 14 | I/O |
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DD14 | 16 | I/O |
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DD15 | 18 | I/O |
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DMARQ | 21 | O | DMA Request | This signal is used with DMACK for DMA transfers. By asserting this signal, the |
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| drive indicates that data is ready to be transfered to and from the host. |
DIOW - | 23 | I | Host I/O Write | Rising edge of Write strobe clocks data from the host data bus to a register on |
STOP |
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| the drive. |
DIOR - | 25 | I | Host I/O Read | Read strobe enables data from a register on the drive onto the host data bus. |
HDMARDY |
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| DMA ready during UltraDMA data in bursts. |
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| Data strobe during UltraDMA data out bursts. |
HSTROBE |
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IORDY | 27 | O | I/O Channel Ready | This signal may be driven low by the drive to insert wait states into host I/O |
DDMARDY |
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| cycles. |
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| DMA ready during UltraDMA data out bursts. |
DSTROBE |
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| Data strobe during UltraDMA data in bursts. |
CSEL | 28 |
| Cable Select | Used for Master/Slave selection via cable. Requires special cabling on host |
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| system and installation of Cable Select jumper. |
DMACK - | 29 | I | DMA Acknowledge | This signal is used with DMARQ for DMA transfers. By asserting this signal, the |
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| host is acknowledging the receipt of data or is indicating that data is available. |
INTRQ | 31 | O | Host Interrupt | Interrupt to the host asserted when the drive requires attention from the host. |
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| Request |
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IOCS16 | 32 |
| Device 16 bit I/O | Obsolete |
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PDIAG - | 34 | I/O | Passed Diagnostic | Output by drive when in Slave mode; Input to drive when in Master mode. |
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DA0 | 35 | I | Host Address Bus | 3 bit binary address from the host to select a register in the drive. |
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DA1 | 33 | I |
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DA2 | 36 | I |
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CS0 - | 37 | I | Host Chip Select 0 | Chip select from the host used to access the Command Block registers in the |
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| drive. This signal is a decode of I/O addresses 1F0 - 1F7 hex. |
CS1 - | 38 | I | Host Chip Select 1 | Chip select from the host used to access the Control registers in the drive. This |
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| signal is a decode of I/O addresses 3F6 - 3F7 hex. |
DASP - | 39 | I/O | Drive Active/Drive | |
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| 1 Present | that |
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| device 1 is present. |
GND | 02 | N/A | Ground | Signal ground. |
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| 19 |
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| 22 |
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| 24 |
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| 26 |
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| 30 |
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| 40 |
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KEY | 20 | N/A | Key | Pin used for keying the interface connector. |
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