J3 PCI Bus Connector
Gigabit Ethernet/82543 PMC Installation and Use 3-7
3
J3 PCI Bus Connector

Table 3-5 on page 3-8 identifies the 32-bit J3 PCI bus connector pin

assignments, respectively. Table 3-6 on page 3-9 defines the signals

associated with the connector pins.

INTA*, INTB*, INTC*,
INTD*
PCI device interrupt request signal
IRDY* PCI device initiator ready signal
LOCK* PCI data exchange bus control line signal
NC No connection
PAR Parity validation signal
PERR* PCI data and address parity error signal
REQ* PCI bus mastering request signal
REQ64* 64-bit transfer request signal
RST* PCI I/O reset signal
SBO* Snoop backoff
SDONE* Snoop done
SERR* PCI system error signal
STOP* PCI device data transfer stop signal
TCK Test clock
TDI JTAG, test data input
TDO JTAG, test data output
TMS TMS Test mode select
TRDY* Target ready
TRST* JTAG, test reset
V(I/O) Voltage I/O source

Table 3-4. J1 and J2 PCI Bus Connector Signal Definitions (Continued)

Signal Definition