© National Instruments Corporation Index-1 Lab-NB User Manual
Index

Numbers/Symbols

+5 V signal (table), 2-7
82C55A Digital I/O Register group, 4-25
to 4-29
control words. See control words.
Digital Control Register, 4-29
digital I/O circuitry block diagram, 3-9
OKI 82C55A data sheet, D-1 to D-17
overview, 4-25
Port A Register, 4-26
Port B Register, 4-27
Port C Register
description, 4-28
pin assignments (figure)
mode 1 input, 4-60
mode 1 output, 4-62
mode 2, 4-64
pin connections, 2-11 to 2-12
resetting of ports A and C
(warning), 2-11
set/reset control words (table), 4-65
signal assignments (table), 2-12
status-word bit definitions
bidirectional data path, 4-64
input, 4-60
output, 4-62
programming. See digital I/O circuitry,
programming.
register map, 4-3
theory of operation, 3-9 to 3-10
8253 Counter/Timer Register groups, 4-16
to 4-24. See also general-purpose timing
signal connections.
AMD 8253 data sheet, C-1 to C-13
Counter A Mode Register, 4-20
Counter A0 Data Register
description, 4-17
programming
controlled acquisition mode, 4-40
to 4-42, 4-47
freerun acquisition mode, 4-43 to
4-44, 4-49
Counter A1 Data Register
description, 4-18
programming
controlled acquisition mode,
4-41, 4-47 to 4-48
freerun acquisition mode,
4-44, 4-50
Counter A2 Data Register
description, 4-19
interrupt programming of analog
output circuitry, 4-54
Counter B Mode Register, 4-24
Counter B0 Data Register
description, 4-21
programming
controlled acquisition mode, 4-40
freerun acquisition mode, 4-43
to 4-44
Counter B1 Data Register, 4-22
Counter B2 Data Register, 4-23
counter block diagram, 3-11
overview, 4-16
register map, 4-3
timing I/O circuitry, 3-10 to 3-11

A

ACH<0..7> signal
description (table), 2-7
input ranges and maximum ratings, 2-8
ACK* signal
description (table), 2-13
mode 1 output timing, 2-15
mode 2 bidirectional timing, 2-16
A/D Clear Register
clearing A/D circuitry, 4-41, 4-44, 4-50
clearing analog input circuitry, 4-39
description, 4-12
A/D Configuration Register
description, 4-6 to 4-8